STE145N65M5

STE145N65M5 N-channel 650 V, 0.012 Ω typ., 143 A MDmesh™ M5 Power MOSFET in an ISOTOP package Datasheet - production data Features Order code VDS @ TJmax RDS(on) max. ID STE145N65M5 710 V 0.015 Ω 143 A     Extremely low RDS(on) Low gate charge and input capacitance Excellent switching performance 100% avalanche tested Applications  Figure 1: Internal schematic diagram Switching applications Description This device is an N-channel Power MOSFET based on the MDmesh™ M5 innovative vertical process technology combined with the wellknown PowerMESH™ horizontal layout. The resulting product offers extremely low onresistance, making it particularly suitable for applications requiring high power and superior efficiency. Table 1: Device summary Order code Marking Package Packaging STE145N65M5 145N65M5 ISOTOP Tube November 2015 DocID025538 Rev 2 This is information on a product in full production. 1/13 www.st.com Contents STE145N65M5 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package information ....................................................................... 9 4.1 5 2/13 ISOTOP package information ......................................................... 10 Revision history ............................................................................ 12 DocID025538 Rev 2 STE145N65M5 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol VGS Parameter Value Unit Gate-source voltage ± 25 V ID Drain current (continuous) at TC = 25 °C 143 A ID Drain current (continuous) at TC = 100 °C 90 A (1) IDM Drain current (pulsed) 572 A PTOT Total dissipation at TC = 25 °C 679 W IAR Avalanche current, repetitive or not repetitive (pulse width limited by Tj max) 12 A EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 2420 mJ Peak diode recovery voltage slope 15 V/ns VISO Isolation withstand voltage applied between each pin and heatsink plate (AC voltage, t = 60 s) 2.5 kV Tstg Storage temperature dv/dt (2) Tj - 55 to 150 Max. operating junction temperature 150 °C Notes: (1) (2) Pulse width limited by safe operating area. ISD ≤ 143 A, di/dt ≤ 400 A/µs; VDS(peak) < V(BR)DSS, VDD = 400 V. Table 3: Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case max Rthj-amb Thermal resistance junction-ambient max DocID025538 Rev 2 Value Unit 0.184 °C/W 30 °C/W 3/13 Electrical characteristics 2 STE145N65M5 Electrical characteristics TC = 25 °C unless otherwise specified Table 4: On/off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage VGS = 0 V, ID = 1 mA Min. Typ. Max. 650 Unit V VGS = 0 V, VDS = 650 V 10 µA VGS = 0 V, VDS = 650 V, TC = 125 °C 100 µA Gate-body leakage current VDS = 0 V, VGS = ±25 V ±100 nA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 4 5 V RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 69 A 0.012 0.015 Ω Min. Typ. Max. Unit - 18500 - pF - 413 - pF - 11 - pF - 415 - pF - 1950 - pF IDSS IGSS Zero gate voltage drain current 3 Table 5: Dynamic Symbol Ciss Parameter Test conditions Input capacitance VDS= 100 V, f = 1 MHz, VGS = 0 V Coss Output capacitance Crss Reverse transfer capacitance (1) Co(er) (2) Co(tr) Equivalent output capacitance energy related Equivalent output capacitance time related VGS = 0, VDS = 0 to 520 V RG Intrinsic gate resistance f = 1 MHz, open drain - 0.7 - Ω Qg Total gate charge - 414 - nC Qgs Gate-source charge - 114 - nC Qgd Gate-drain charge VDD = 520 V, ID = 69 A, VGS = 10 V (see Figure 15: "Test circuit for gate charge behavior") - 164 - nC Notes: (1) Co(er) is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS increases from 0 to 80% VDSS (2) Co(tr) is defined as a constant equivalent capacitance giving the same charging time as C oss when VDS increases from 0 to 80% VDSS 4/13 DocID025538 Rev 2 STE145N65M5 Electrical characteristics Table 6: Switching times Symbol Parameter td(V) Voltage delay time tr(V) Voltage rise time tf(i) Current fall time tC(off) Crossing time Test conditions Min. Typ. Max. Unit VDD = 400 V, ID = 85 A RG = 4.7 Ω, VGS = 10 V (see Figure 16: "Test circuit for inductive load switching and diode recovery times" and Figure 19: "Switching time waveform") - 255 - ns - 11 - ns - 82 - ns - 88 - ns Min. Typ. Max. Unit Table 7: Source drain diode Symbol ISD Parameter Test conditions Source-drain current - 143 A (1) Source-drain current (pulsed) - 572 A (2) Forward on voltage VGS = 0 V, ISD = 143 A - 1.5 V trr Reverse recovery time - 568 ns Qrr Reverse recovery charge - 14.5 µC IRRM Reverse recovery current ISD = 143 A, di/dt = 100 A/µs, VDD = 100 V (see Figure 16: "Test circuit for inductive load switching and diode recovery times") - 51 A ISD = 143 A, di/dt = 100 A/µs, VDD = 100 V, Tj = 150 °C (see Figure 16: "Test circuit for inductive load switching and diode recovery times") - 728 ns - 24.5 µC - 67 A ISDM, VSD trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current Notes: (1) (2) Pulse width is limited by safe operating area Pulsed: pulse duration = 300 µs, duty cycle 1.5% DocID025538 Rev 2 5/13 Electrical characteristics 2.2 STE145N65M5 Electrical characteristics (curves) Figure 3: Thermal impedance Figure 2: Safe operating area Figure 5: Transfer characteristics Figure 4: Output characteristics AM17901v1 ID (A) VGS=10V 9V 300 8V 250 200 150 7V 100 50 6V 0 0 5 10 15 20 25 VDS(V) Figure 6: Gate charge vs gate-source voltage 6/13 Figure 7: Static drain-source on-resistance DocID025538 Rev 2 STE145N65M5 Electrical characteristics Figure 9: Normalized gate threshold voltage vs temperature Figure 8: Capacitance variations C (pF) 100000 Ciss 10000 1000 Coss f=1 MHz 100 10 Crss 1 0.1 1 10 100 VDS(V) Figure 10: Normalized on-resistance vs temperature Figure 11: Normalized V(BR)DSS vs temperature Figure 12: Output capacitance stored energy Figure 13: Switching losses vs gate resistance The previous figure Eon includes reverse recovery of a SiC diode. DocID025538 Rev 2 7/13 Test circuits 3 STE145N65M5 Test circuits Figure 14: Test circuit for resistive load switching times Figure 15: Test circuit for gate charge behavior Figure 16: Test circuit for inductive load switching and diode recovery times Figure 17: Unclamped inductive load test circuit Figure 18: Unclamped inductive waveform Figure 19: Switching time waveform AM05540v2_for_M5 8/13 DocID025538 Rev 2 STE145N65M5 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK is an ST trademark. DocID025538 Rev 2 9/13 Package information 4.1 STE145N65M5 ISOTOP package information Figure 20: ISOTOP outline 10/13 DocID025538 Rev 2 STE145N65M5 Package information Table 8: ISOTOP mechanical data mm Dim. Min. Typ. Max. A 11.80 12.20 A1 8.90 9.10 B 7.80 8.20 C 0.75 0.85 C2 1.95 2.05 D 37.80 38.20 D1 31.50 31.70 E 25.15 25.50 E1 23.85 24.15 E2 24.80 G 14.90 15.10 G1 12.60 12.80 G2 3.50 4.30 F 4.10 4.30 F1 4.60 5 ØP 4 4.30 P1 4 4.40 S 30.10 30.30 DocID025538 Rev 2 11/13 Revision history 5 STE145N65M5 Revision history Table 9: Document revision history Date Revision 18-Nov-2013 1 First release. 2 Updated title, features and description on cover page. Document status promoted from preliminary to production data. Modified: Table 2: "Absolute maximum ratings" and Figure 12: "Output capacitance stored energy" Minor text changes. 12-Nov-2015 12/13 Changes DocID025538 Rev 2 STE145N65M5 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved DocID025538 Rev 2 13/13