STE40NK90ZD

STE40NK90ZD N-CHANNEL 900V - 0.14Ω - 40 A ISOTOP Super FREDMesh™ MOSFET Figure 1: Package Table 1: General Features TYPE VDSS RDS(on) ID Pw STE40NK90ZD 900 V < 0.18 Ω 40 A 600 W ■ ■ ■ ■ ■ ■ TYPICAL RDS(on) = 0.14 Ω EXTREMELY HIGH dv/dt CAPABILITY 100% AVALANCHE TESTED GATE CHARGE MINIMIZED VERY LOW INTRINSIC CAPACITANCES VERY GOOD MANUFACTURING REPEATIBILITY DESCRIPTION The SuperFREDMesh™ series is obtained through an extreme optimization of ST’s well established strip-based PowerMESH™ layout. In addition to pushing on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the most demanding applications. Such series complements ST full range of high voltage MOSFETs including revolutionary MDmesh™ products. ISOTOP Figure 2: Internal Schematic Diagram APPLICATIONS ■ HIGH CURRENT, HIGH SPEED SWITCHING ■ IDEAL FOR WELDING EQUIPMENT Table 2: Order Codes SALES TYPE MARKING PACKAGE PACKAGING STE40NK90ZD E40NK90ZD ISOTOP TUBE Rev. 4 December 2004 1/10 STE40NK90ZD Table 3: Absolute Maximum ratings Symbol VDS VDGR VGS Parameter Value Unit Drain-source Voltage (VGS = 0) 900 V Drain-gate Voltage (RGS = 20 kΩ) 900 V Gate- source Voltage ± 30 V ID Drain Current (continuous) at TC = 25°C 40 A ID Drain Current (continuous) at TC = 100°C 25 A IDM (
) Drain Current (pulsed) 160 A PTOT Total Dissipation at TC = 25°C VESD(G-S) dv/dt (1) 600 W Derating Factor 5 W/°C Gate source ESD(HBM-C=100pF, R=1.5KΩ) 7 KV Peak Diode Recovery voltage slope VISO Insulation Withstand Voltage (AC-RMS) from All Four Terminals to External Heatsink Tj Tstg Operating Junction Temperature Storage Temperature 8 V/ns 2500 V - 65 to 150 °C (
) Pulse width limited by safe operating area (1) ISD ≤ 40A, di/dt ≤ 500 A/µs, VDD ≤ V(BR)DSS. Table 4: Thermal Data Rthj-case Thermal Resistance Junction-case Max 0.2 °C/W Rthj-amb Thermal Resistance Junction-ambient Max 40 °C/W Table 5: Avalanche Characteristics Symbol Max. Value Unit IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) Parameter 40 A EAS Single Pulse Avalanche Energy (starting Tj = 25 °C, ID = IAR, VDD = 35 V) 1.2 J Table 6: Gate-Source Zener Diode Symbol BVGSO Parameter Gate-Source Breakdown Voltage Test Conditions Min. Igs=± 1mA (Open Drain) 30 Typ. Max. Unit V PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the usage of external components. 2/10 STE40NK90ZD ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED) Table 7: On/Off Symbol Parameter Test Conditions Min. Typ. Max. 900 Unit Drain-source Breakdown Voltage ID = 1 mA, VGS = 0 IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating VDS = Max Rating, TC = 125 °C 10 100 µA µA IGSS Gate-body Leakage Current (VDS = 0) VGS = ± 20V ±10 µA VGS(th) Gate Threshold Voltage VDS = VGS, ID = 150µA 3.75 4.5 V RDS(on) Static Drain-source On Resistance VGS = 10V, ID = 20 A 0.14 0.18 Ω Typ. Max. Unit V(BR)DSS 2.5 V Table 8: Dynamic Symbol gfs (1) Ciss Coss Crss Coss eq. (3) Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Conditions Min. VDS = 15V, ID = 20 A VDS = 25V, f = 1 MHz, VGS = 0 35 S 25000 1450 280 pF pF pF Equivalent Output Capacitance VGS = 0V, VDS = 0V to 720V 720 pF td(on) tr td(off) tf Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time VDD = 450 V, ID = 18 A RG = 4.7Ω , VGS = 10 V (Figure 17) 92 102 450 200 ns ns ns ns Qg Qgs Qgd Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD = 720 V, ID = 36 A, VGS = 10V 590 89 323 826 nC nC nC Typ. Max. Unit 40 160 A A 1.6 V Table 9: Source Drain Diode Symbol Parameter Test Conditions Min. ISD ISDM (2) Source-drain Current Source-drain Current (pulsed) VSD (1) Forward On Voltage ISD = 40 A, VGS = 0 Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 36 A, di/dt = 100 A/µs VDD = 50 V, Tj = 25°C (Figure 18) 450 3.6 16.2 ns µC A Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 36 A, di/dt = 100 A/µs VDD = 50 V, Tj = 150°C (Figure 18) 930 12 26 ns µC A trr Qrr IRRM trr Qrr IRRM Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. 3. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. 3/10 STE40NK90ZD Figure 3: Safe Operating Area Figure 6: Thermal Impedance Figure 4: Output Characteristics Figure 7: Transfer Characteristics Figure 5: Transconductance Figure 8: Static Drain-source On Resistance 4/10 STE40NK90ZD Figure 9: Gate Charge vs Gate-source Voltage Figure 12: Capacitance Variations Figure 10: Normalized Gate Thereshold Voltage vs Temperature Figure 13: Normalized On Resistance vs Temperature Figure 11: Source-Drain Diode Forward Characteristics Figure 14: Normalized BVdss vs Temperature 5/10 STE40NK90ZD Figure 15: Avalanche Energy vs Starting Tj 6/10 STE40NK90ZD Figure 16: Unclamped Inductive Load Test Circuit Figure 19: Unclamped Inductive Wafeform Figure 17: Switching Times Test Circuit For Resistive Load Figure 20: Gate Charge Test Circuit Figure 18: Test Circuit For Inductive Load Switching and Diode Recovery Times 7/10 STE40NK90ZD ISOTOP MECHANICAL DATA mm DIM. MIN. TYP. inch MAX. MIN. TYP. MAX. A 11.8 12.2 0.466 0.480 B 8.9 9.1 0.350 0.358 C 1.95 2.05 0.076 0.080 D 0.75 0.85 0.029 0.033 E 12.6 12.8 0.496 0.503 F 25.15 25.5 0.990 1.003 G 31.5 31.7 1.240 1.248 H 4 J 4.1 4.3 0.161 0.157 0.169 K 14.9 15.1 0.586 0.594 L 30.1 30.3 1.185 1.193 M 37.8 38.2 1.488 1.503 N 4 O 7.8 0.157 8.2 0.307 0.322 A G B O H J K L M 8/10 C F E D N STE40NK90ZD Table 10: Revision History Date Revision 05-Jul-2004 15-Oct-2004 04-Nov-2004 13-Dec-2004 1 2 3 4 Description of Changes First Release. New value inserted in table 3. (VISO ) Preliminary Version Final datasheet 9/10 STE40NK90ZD Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners © 2004 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 10/10