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STE48NM50

STE48NM50

  • 厂商:

    STMICROELECTRONICS(意法半导体)

  • 封装:

    ISOTOP

  • 描述:

    MOSFET N-CH 550V 48A ISOTOP

  • 数据手册
  • 价格&库存
STE48NM50 数据手册
STE48NM50 N-CHANNEL 550V @ Tjmax - 0.08Ω - 48A ISOTOP MDmesh™ MOSFET Table 1: General Features TYPE VDSS (@Tjmax) RDS(on) ID 550V < 0.1Ω 48 A STE48NM50 ■ ■ ■ ■ ■ ■ Figure 1: Package TYPICAL RDS(on) = 0.08Ω HIGH dv/dt AND AVALANCHE CAPABILITIES 100% AVALANCHE TESTED LOW INPUT CAPACITANCE AND GATE CHARGE LOW GATE INPUT RESISTANCE TIGHT PROCESS CONTROL AND HIGH MANUFACTURING YIELDS DESCRIPTION The MDmesh™ is a new revolutionary MOSFET technology that associates the Multiple Drain process with the Company’s PowerMESH™ horizontal layout. The resulting product has an outstanding low on-resistance, impressively high dv/dt and excellent avalanche characteristics. The adoption of the Company’s proprietary strip technique yields overall dynamic performance that is significantly better than that of similar competition’s products. ISOTOP Figure 2: Internal Schematic Diagram APPLICATIONS The MDmesh™ family is very suitable for increasing power density of high voltage converters allowing system miniaturization and higher efficiencies. Table 2: Order Codes SALES TYPE MARKING PACKAGE PACKAGING STE48NM50 E48NM50 ISOTOP TUBE Rev. 2 March 2005 1/9 STE48NM50 Table 3: Absolute Maximum ratings Symbol Value Unit Gate- source Voltage ±30 V ID Drain Current (continuous) at TC = 25°C 48 A ID Drain Current (continuous) at TC = 100°C 30 A Drain Current (pulsed) 192 A Total Dissipation at TC = 25°C 450 W Derating Factor 3.6 W/°C Peak Diode Recovery voltage slope 15 V/ns 2500 V –65 to 150 °C 150 °C 0.28 °C/W 0.05 °C/W Max Value Unit 15 A 810 mJ VGS IDM () PTOT dv/dt (*) Parameter VISO Insulation Winthstand Voltage (AC-RMS) Tstg Storage Temperature Tj Max. Operating Junction Temperature ()Pulse width limited by safe operating area (*) ISD ≤ 48A, di/dt ≤ 400 A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX. Table 4: Thermal Data Rthj-case Thermal Resistance Junction-case Rthc-sink (**) Thermal Resistance Case-sink Max Typ (**) with conductive GREASE Applies Table 5: Avalanche Characteristics Symbol Parameter IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) EAS Single Pulse Avalanche Energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED) Table 6: On/Off Symbol Test Conditions Min. Typ. Max. Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating 10 µA VDS= Max Rating, TC= 125°C 100 µA Gate-body Leakage Current (VDS = 0) VGS = ± 30V ±100 nA VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250µA 4 5 V RDS(on) Static Drain-source On Resistance VGS = 10V, ID = 24A 0.08 0.1 Ω IGSS 500 Unit ID = 250 µA, VGS = 0 IDSS 2/9 Parameter Drain-source Breakdown Voltage V(BR)DSS 3 V STE48NM50 ELECTRICAL CHARACTERISTICS (CONTINUED) Table 7: Dynamic Symbol gfs (1) Parameter Test Conditions Forward Transconductance VDS > ID(on) x RDS(on)max, ID = 24A Input Capacitance Output Capacitance Reverse Transfer Capacitance VDS = 25V, f = 1 MHz, VGS = 0 Gate Input Resistance td(on) tr td(off) tf tc Qg Qgs Qgd Ciss Coss Crss RG Min. Typ. Max. Unit 20 S 3700 610 80 pF pF pF f=1 MHz Gate DC Bias = 0 Test Signal Level = 20mV Open Drain 1.7 Ω Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Cross-over Time VDD = 250V, ID = 24 A RG = 4.7Ω VGS = 10 V (see Figure 14) 40 35 18 23 44 ns ns ns ns ns Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD = 400V, ID = 48 A, VGS = 10V (see Figure 18) 87 23 42 117 nC nC nC Typ. Max. Unit 48 A 192 A 1.5 V Table 8: Source Drain Diode Symbol ISD ISDM (2) VSD (1) Parameter Test Conditions Min. Source-drain Current Source-drain Current (pulsed) Forward On Voltage ISD = 48 A, VGS = 0 trr Qrr Irrm Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 40 A, di/dt = 100 A/µs, VDD = 100 V, Tj = 25°C (see Figure 16) 520 7.8 30 ns µC A trr Qrr Irrm Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 40 A, di/dt = 100 A/µs, VDD = 100 V, Tj = 150°C (see Figure 16) 680 11.2 33 ns µC A Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. 3/9 STE48NM50 Figure 3: Safe Operating Area Figure 6: Thermal Impedance Figure 4: Output Characteristics Figure 7: Transfer Characteristics Figure 5: Transconductance Figure 8: Static Drain-source On Resistance 4/9 STE48NM50 Figure 9: Gate Charge vs Gate-source Voltage Figure 12: Capacitance Variations Figure 10: Normalized Gate Thereshold Voltage vs Temperature Figure 13: Normalized On Resistance vs Temperature Figure 11: Source-Drain Diode Forward Characteristics 5/9 STE48NM50 Figure 14: Unclamped Inductive Load Test Circuit Figure 17: Unclamped Inductive Wafeform Figure 15: Switching Times Test Circuit For Resistive Load Figure 18: Gate Charge Test Circuit Figure 16: Test Circuit For Inductive Load Switching and Diode Recovery Times 6/9 STE48NM50 ISOTOP MECHANICAL DATA mm DIM. MIN. TYP. inch MAX. MIN. A 11.8 12.2 0.466 TYP. MAX. 0.480 B 8.9 9.1 0.350 0.358 C 1.95 2.05 0.076 0.080 D 0.75 0.85 0.029 0.033 E 12.6 12.8 0.496 0.503 F 25.15 25.5 0.990 1.003 G 31.5 31.7 1.240 1.248 H 4 0.157 J 4.1 4.3 0.161 0.169 K 14.9 15.1 0.586 0.594 L 30.1 30.3 1.185 1.193 M 37.8 38.2 1.488 1.503 8.2 0.307 N 4 O 7.8 0.157 0.322 A G B O F E H D N J K C L M 7/9 STE48NM50 Table 9: Revision History 8/9 Date Revision 30/Mar/2005 2 Description of Changes Modified value in table 7 STE48NM50 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners © 2005 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 9/9
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