STE48NM60

STE48NM60 N-CHANNEL 650V @ Tjmax - 0.09Ω - 48A ISOTOP MDmesh™ MOSFET Table 1: General Features TYPE Figure 1: Package VDSS (@Tjmax) RDS(on) ID 650V < 0.11Ω 48 A STE48NM60 ) s ( t c u d o s) r ( P t c e u t e l od o s Pr b O ete l ) o s ( s t b c u -O d o s) r P ( t e uc t e l od o s Pr b O te e l o s b ■ ■ ■ ■ ■ ■ TYPICAL RDS(on) = 0.09Ω HIGH dv/dt AND AVALANCHE CAPABILITIES 100% AVALANCHE TESTED LOW INPUT CAPACITANCE AND GATE CHARGE LOW GATE INPUT RESISTANCE TIGHT PROCESS CONTROL AND HIGH MANUFACTURING YIELDS DESCRIPTION The MDmesh™ is a new revolutionary MOSFET technology that associates the Multiple Drain process with the Company’s PowerMESH™ horizontal layout. The resulting product has an outstanding low on-resistance, impressively high dv/dt and excellent avalanche characteristics. The adoption of the Company’s proprietary strip technique yields overall dynamic performance that is significantly better than that of similar competition’s products. ISOTOP Figure 2: Internal Schematic Diagram APPLICATIONS The MDmesh™ family is very suitable for increasing power density of high voltage converters allowing system miniaturization and higher efficiencies. Table 2: Order Codes O SALES TYPE MARKING PACKAGE PACKAGING STE48NM60 E48NM60 ISOTOP TUBE Rev. 2 March 2005 1/9 STE48NM60 Table 3: Absolute Maximum ratings Symbol Value Unit Gate- source Voltage ±30 V ID Drain Current (continuous) at TC = 25°C 48 A ID Drain Current (continuous) at TC = 100°C 30 A IDM (
) Drain Current (pulsed) 192 A PTOT Total Dissipation at TC = 25°C 450 W Derating Factor 3.57 W/°C 15 V/ns 2500 V –65 to 150 °C 150 °C 0.28 °C/W 30 °C/W 300 °C Max Value Unit VGS dv/dt (1) Parameter Peak Diode Recovery voltage slope VISO Insulation Winthstand Voltage (AC-RMS) Tstg Storage Temperature ) s ( t c u d o s) r ( P t c e u t e l od o s Pr b O ete l ) o s ( s t b c u -O d o s) r P ( t e uc t e l od o s Pr b O te e l o s b Tj Max. Operating Junction Temperature (
)Pulse width limited by safe operating area (1) ISD ≤ 48A, di/dt ≤ 400 A/µs, VDD ≤ V(BR)DSS, T j ≤ T JMAX. Table 4: Thermal Data Rthj-case Thermal Resistance Junction-case Rthj-amb Thermal Resistance Junction-ambient Tl Max Max Maximum Lead Temperature For Soldering Purpose (*) with conductive GREASE Applies Table 5: Avalanche Characteristics Symbol Parameter IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) 15 A EAS Single Pulse Avalanche Energy (starting Tj = 25 °C, ID = IAR, VDD = 35 V) 850 mJ ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED) Table 6: On/Off Symbol Min. Typ. Max. 600 Unit Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating 10 µA VDS= Max Rating, TC= 125°C 100 µA Gate-body Leakage Current (VDS = 0) VGS = ±30V ±100 nA VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250µA 4 5 V RDS(on) Static Drain-source On Resistance VGS = 10V, ID = 22.5A 0.09 0.11 Ω IGSS 2/9 Test Conditions ID = 250 µA, VGS = 0 IDSS O Parameter Drain-source Breakdown Voltage V(BR)DSS 3 V STE48NM60 ELECTRICAL CHARACTERISTICS (CONTINUED) Table 7: Dynamic Symbol gfs (1) Ciss Coss Crss Coss eq. (2) RG Parameter Test Conditions Forward Transconductance VDS > ID(on) x RDS(on)max, ID = 24A Input Capacitance Output Capacitance Reverse Transfer Capacitance Min. Typ. Max. Unit 20 S VDS = 25V, f = 1 MHz, VGS = 0 3800 1250 80 pF pF pF Equivalent Output Capacitance VGS = 0V, VDS = 0V to 480V 340 pF Gate Input Resistance f=1 MHz Gate DC Bias = 0 Test Signal Level = 20mV Open Drain 1.4 Ω ) s ( t c u d o s) r ( P t c e u t e l od o s Pr b O ete l ) o s ( s t b c u -O d o s) r P ( t e uc t e l od o s Pr b O te e l o s b td(on) tr Turn-on Delay Time Rise Time VDD = 250V, ID = 22.5A RG = 4.7Ω VGS = 10V (see Figure 14) 30 20 ns ns tr(Voff) tf tc Off-voltage Rise Time Fall Time Cross-over Time VDD = 400V, ID = 45A, RG = 4.7Ω, VGS = 10V 16 23 40 ns ns ns Qg Qgs Qgd Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD = 400V, ID = 45A, VGS = 10V (see Figure 18) 96 31 43 134 nC nC nC Typ. Max. Unit Table 8: Source Drain Diode Symbol ISD Parameter Test Conditions Min. Source-drain Current 48 A ISDM (2) Source-drain Current (pulsed) 192 A VSD (1) Forward On Voltage ISD = 45A, VGS = 0 1.5 V Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 45A, di/dt = 100A/µs, VDD = 100 V, Tj = 25°C (see Figure 16) 508 10 40 ns µC A Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 45A, di/dt = 100A/µs, VDD = 100 V, Tj = 150°C (see Figure 16) 650 14 43 ns µC A trr Qrr IRRM trr Qrr IRRM 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS O 3/9 STE48NM60 Figure 3: Safe Operating Area Figure 6: Thermal Impedance ) s ( t c u d o s) r ( P t c e u t e l od o s Pr b O ete l ) o s ( s t b c u -O d o s) r P ( t e uc t e l od o s Pr b O te e l o s b Figure 4: Output Characteristics Figure 7: Transfer Characteristics Figure 5: Transconductance Figure 8: Static Drain-source On Resistance O 4/9 STE48NM60 Figure 9: Gate Charge vs Gate-source Voltage Figure 12: Capacitance Variations ) s ( t c u d o s) r ( P t c e u t e l od o s Pr b O ete l ) o s ( s t b c u -O d o s) r P ( t e uc t e l od o s Pr b O te e l o s b Figure 10: Normalized Gate Thereshold Voltage vs Temperature Figure 13: Normalized On Resistance vs Temperature Figure 11: Source-Drain Diode Forward Characteristics O 5/9 STE48NM60 Figure 14: Unclamped Inductive Load Test Circuit Figure 17: Unclamped Inductive Wafeform ) s ( t c u d o s) r ( P t c e u t e l od o s Pr b O ete l ) o s ( s t b c u -O d o s) r P ( t e uc t e l od o s Pr b O te e l o s b Figure 15: Switching Times Test Circuit For Resistive Load Figure 16: Test Circuit For Inductive Load Switching and Diode Recovery Times O 6/9 Figure 18: Gate Charge Test Circuit STE48NM60 ISOTOP MECHANICAL DATA mm DIM. MIN. TYP. inch MAX. MIN. A 11.8 12.2 0.466 TYP. MAX. 0.480 B 8.9 9.1 0.350 0.358 C 1.95 2.05 0.076 0.080 D 0.75 0.85 0.029 0.033 E 12.6 12.8 0.496 0.503 ) s ( t c u d o s) r ( P t c e u t e l od o s Pr b O ete l ) o s ( s t b c u -O d o s) r P ( t e uc t e l od o s Pr b O te e l o s b F 25.15 25.5 0.990 1.003 G 31.5 31.7 1.240 1.248 H 4 0.157 J 4.1 4.3 0.161 0.169 K 14.9 15.1 0.586 0.594 L 30.1 30.3 1.185 1.193 M 37.8 38.2 1.488 1.503 8.2 0.307 N 4 O 7.8 0.157 0.322 A G B O F E H D N O J K C L M 7/9 STE48NM60 Table 9: Revision History Date Revision 30/Mar/2005 2 Description of Changes Modified value in table 7 ) s ( t c u d o s) r ( P t c e u t e l od o s Pr b O ete l ) o s ( s t b c u -O d o s) r P ( t e uc t e l od o s Pr b O te e l o s b O 8/9 STE48NM60 ) s ( t c u d o s) r ( P t c e u t e l od o s Pr b O ete l ) o s ( s t b c u -O d o s) r P ( t e uc t e l od o s Pr b O te e l o s b Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. O The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners © 2005 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 9/9