STE70NM50

STE70NM50 N-CHANNEL 500V - 0.045Ω - 70A ISOTOP Zener-Protected MDmesh™Power MOSFET TYPE STE70NM50 n n n n n n n VDSS RDS(on) ID 500V < 0.05Ω 70 A TYPICAL RDS(on) = 0.045Ω HIGH dv/dt AND AVALANCHE CAPABILITIES IMPROVED ESD CAPABILITY LOW INPUT CAPACITANCE AND GATE CHARGE LOW GATE INPUT RESISTANCE TIGHT PROCESS CONTROL INDUSTRY’S LOWEST ON-RESISTANCE DESCRIPTION The MDmesh™ is a new revolutionary MOSFET technology that associates the Multiple Drain process with the Company’s PowerMESH™ horizontal layout. The resulting product has an outstanding low on-resistance, impressively high dv/dt and excellent avalanche characteristics. The adoption of the Company’s proprietary strip technique yields overall dynamic performance that is significantly better than that of similar competition’s products. ) s t( c u d o r P ISOTOP e t le o s b O ) INTERNAL SCHEMATIC DIAGRAM s ( t c u d o APPLICATIONS The MDmesh™ family is very suitable for increasing power density of high voltage converters allowing system miniaturization and higher efficiencies. r P e t e l o s b O ABSOLUTE MAXIMUM RATINGS Symbol Value Unit Drain-source Voltage (VGS = 0) 500 V Drain-gate Voltage (RGS = 20 kΩ) 500 V Gate- source Voltage ±30 V ID Drain Current (continuous) at TC = 25°C 70 A ID Drain Current (continuous) at TC = 100°C 44 A Drain Current (pulsed) 280 A Total Dissipation at TC = 25°C VDS VDGR VGS IDM (l) PTOT VESD(G-S) dv/dt (1) Tstg Tj Parameter 600 W Gate source ESD(HBM-C=100pF, R=15KΩ) 6 KV Derating Factor 5 W/°C Peak Diode Recovery voltage slope Storage Temperature Max. Operating Junction Temperature (•)Pulse width limited by safe operating area September 2002 15 V/ns –65 to 150 °C 150 °C (1)ISD ≤60A, di/dt ≤400A/µs, V DD ≤ V(BR)DSS, Tj ≤ T JMAX 1/8 STE70NM50 THERMAL DATA Rthj-case Thermal Resistance Junction-case Max 0.2 °C/W Rthj-amb Thermal Resistance Junction-ambient Max 30 °C/W 300 °C Tl Maximum Lead Temperature For Soldering Purpose AVALANCHE CHARACTERISTICS Symbol Max Value Unit IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) Parameter 30 A EAS Single Pulse Avalanche Energy (starting Tj = 25 °C, ID = IAR, VDD = 35 V) 1.4 J ) s t( ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED) OFF Symbol Parameter Test Conditions Drain-source Breakdown Voltage ID = 250 µA, VGS = 0 IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating IGSS Gate-body Leakage Current (VDS = 0) VGS = ± 20V V(BR)DSS Parameter VGS(th) Gate Threshold Voltage RDS(on) Static Drain-source On Resistance u d o r P e DYNAMIC let Symbol gfs (1) o s b O eP Test Conditions Test Conditions VDS > ID(on) x RDS(on)max, ID = 30A VDS = 25V, f = 1 MHz, VGS = 0 Max. Unit V 10 µA 100 µA ± 10 µA Min. Typ. Max. Unit 3 4 5 V 0.045 0.05 Ω Typ. Max. Unit VGS = 10V, ID = 30A Min. 35 S Ciss Input Capacitance 7500 pF Coss Output Capacitance 980 pF Crss Reverse Transfer Capacitance 200 pF RG Gate Input Resistance 1.5 Ω f=1 MHz Gate DC Bias = 0 Test Signal Level = 20mV Open Drain Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2/8 o s b VDS = VGS, ID = 250µA Parameter Forward Transconductance ro let O ) s ( t c c u d Typ. 500 VDS = Max Rating, TC = 125 °C ON (1) Symbol Min. STE70NM50 ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON Symbol td(on) tr Parameter Test Conditions Rise Time Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge Min. Typ. VDD = 250V, ID = 30A RG = 4.7Ω VGS = 10V (see test circuit, Figure 3) Turn-on Delay Time VDD = 400V, ID = 60A, VGS = 10V Max. Unit 51 ns 58 ns 190 266 nC 53 nC 97 nC ) s t( SWITCHING OFF Symbol tr(Voff) Parameter Test Conditions VDD = 400V, ID = 60A, RG = 4.7Ω, VGS = 10V (see test circuit, Figure 5) Off-voltage Rise Time tf Fall Time tc Cross-over Time Min. od 46 ISD Pr 108 Parameter Test Conditions e t le so Source-drain Current Ob Max. uc 51 SOURCE DRAIN DIODE Symbol Typ. Min. Typ. Unit ns ns ns Max. Unit 60 A 240 A 1.5 V ISDM (2) Source-drain Current (pulsed) VSD (1) Forward On Voltage ISD = 60A, VGS = 0 trr Qrr Irrm Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 60A, di/dt = 100A/µs, VDD = 100 V, Tj = 25°C (see test circuit, Figure 5) 532 9.9 37 ns µC A trr Qrr Irrm Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 60A, di/dt = 100A/µs, VDD = 100 V, Tj = 150°C (see test circuit, Figure 5) 636 13.4 42 ns µC A )- s ( t c u d o r P e Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. t e l o GATE-SOURCE ZENER DIODE bs Symbol O BVGSO Parameter Gate-Source Breakdown Voltage Test Conditions Igs=± 1mA (Open Drain) Min. 30 Typ. Max. Unit V PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the 25V Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the usage of external components. 3/8 STE70NM50 Safe Operating Area Thermal Impedance ) s t( c u d Output Characteristics o r P Transfer Characteristics e t le o s b O ) s ( t c u d o r P e t e l o bs Transconductance O 4/8 Static Drain-source On Resistance STE70NM50 Gate Charge vs Gate-source Voltage Capacitance Variations ) s t( c u d Normalized Gate Threshold Voltage vs Temp. o r P Normalized On Resistance vs Temperature e t le o s b O ) s ( t c u d o r P e t e l o s b O Source-drain Diode Forward Characteristics 5/8 STE70NM50 Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform ) s t( c u d Fig. 3: Switching Times Test Circuit For Resistive Load e t le o s b O ) s ( t c u d o r P e t e l o s b O Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/8 o r P Fig. 4: Gate Charge test Circuit STE70NM50 ISOTOP MECHANICAL DATA mm DIM. MIN. inch MAX. MIN. A 11.8 TYP. 12.2 0.466 0.480 B 8.9 9.1 0.350 0.358 C 1.95 2.05 0.076 D 0.75 0.85 0.029 E 12.6 12.8 0.496 F 25.15 25.5 0.990 G 31.5 31.7 H 4 J 4.1 4.3 K 14.9 15.1 L 30.1 30.3 M 37.8 N 4 7.8 s b O )- 8.2 e t e 1.248 0.169 0.594 1.193 1.488 1.503 0.157 0.307 0.322 A B O F E D N H s b O 1.003 1.185 G o r P Pr 0.503 0.586 s ( t c du uc od 0.161 38.2 ) s t( 0.033 1.240 ol MAX. 0.080 0.157 O e t e ol TYP. J K C L M 7/8 STE70NM50 ) s t( c u d e t le o r P o s b O ) s ( t c u d o r P e t e l o s b O Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. © The ST logo is a registered trademark of STMicroelectronics © 2002 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. © http://www.st.com 8/8