STEF01FTR

STEF01 Datasheet 8 V to 48 V fully programmable universal electronic fuse Features HTSSOP14 Maturity status link STEF01 Device summary Order code STEF01FTR Package HTSSOP14 Packing Tape and reel • • • • • • • • • • • • • • • • Operating input voltage range: 8 to 48 V Absolute maximum input voltage: 55 V Continuous current typ.: 4 A N-channel on-resistance typ.: 30 mΩ Enable/fault functions Output clamp voltage: adjustable from 10 to 52 V Programmable undervoltage lockout Short-circuit current limit Programmable overload current limit Adjustable soft-start time Latch or auto-retry thermal protection Maximum allowable power protection Power Good Drives an optional external reverse current protection MOSFET Operating junction temperature -40 °C to 125 °C HTSSOP14 package Applications • • • • • Hot board insertion Electronic circuit breaker/power busing Industrial/alarm/lighting systems Distributed power systems Telecom power modules Description The STEF01 is a universal integrated electronic fuse optimized for monitoring output current and the input voltage on DC power lines. When connected in series to the main power rail, it is able to detect and react to overcurrent and overvoltage conditions. When an overload condition occurs, the device limits the output current to a safe value defined by the user. If the anomalous overload condition persists, the device goes into an open state, disconnecting the load from the power supply. The device is fully programmable. UVLO, overvoltage clamp and start-up time can be set by means of external components. The adjustable turn-on time is useful to keep the in-rush current under control during startup and hot-swap operations. The device provides either thermal latch and autoretry protection modes, which are selectable by means of a dedicated pin. The STEF01 provides a gate driver pin for an external power MOSFET to implement a reverse-current blocking circuit. The intervention of the thermal protection is signaled to the board monitoring circuits through a signal on the fault pin. DS12147 - Rev 7 - April 2022 For further information contact your local STMicroelectronics sales office. www.st.com STEF01 Device block diagram 1 Device block diagram Figure 1. Block diagram GIPD010220161057MT DS12147 - Rev 7 page 2/27 STEF01 Pin configuration 2 Pin configuration Figure 2. Pin configuration (top view ) 1 14 Expos e d pa d 7 8 HTSSOP14 GIPD010220161207MT Table 1. Pin description Pin n° Symbol Note 1 UVLO A resistor divider connected between this pin, Vcc and GND sets the UVLO threshold. If left floating the UVLO is preset to 14.5 V. 2 dv/dt The internal dv/dt circuit controls the slew rate of the output voltage at turn-on. The internal capacitor allows a ramp-up time of around 3 ms. An external capacitor can be added to this pin to increase the ramp-up time. If an additional capacitor is not required, this pin should be left open. 3 GND Ground pin. 4 Auto This pin selects the thermal protection behavior. The device is set in latched mode when this pin is left floating or connected to a voltage higher than 1 V. It is set in auto-retry mode when the pin is connected to GND. A resistor divider connected between this pin, VOUT and GND sets the overvoltage clamp level. If left floating the clamp is preset to 28 V. 5 Vclamp 6, 7, 8, 9 VOUT Output port. All the pins must be tied together with short copper tracks. 10 I-Limit A resistor between this pin and VOUT sets the overload current limit level. 11 Vg Gate driver output for the optional external reverse-blocking MOSFET. Tri-state, bi-directional pin. During normal operation the pin must be left floating, or it can be used to disable the output of the device by pulling it to ground using an open drain or open collector device. DS12147 - Rev 7 12 En/Fault 13 PG Power Good flag. It is an open drain, to be pulled up through an external resistor. 14 VCC Input port. Connect this pin to the exposed pad. Exposed pad VCC Exposed pad. Input port of the device, internally connected to the power element drain. If a thermal fault occurs, the voltage on this pin will go to an intermediate state to signal a monitoring circuit that the device is in thermal shutdown. It can be connected to another device of this family to cause a simultaneous shutdown during thermal events. page 3/27 STEF01 Maximum ratings 3 Maximum ratings Table 2. Absolute maximum ratings Symbol Parameter Value Unit VCC Positive power supply voltage -0.3 to 55 V VOUT/source Output voltage pin -0.3 to VCC V I-Limit Current sense resistor pin -0.3 to VCC V ID Continuous current 6 A PG Power good flag pin -0.3 to VCC V Vclamp, UVLO Vclamp, UVLO pins -0.3 to 7 V En/Fault Enable/Fault pin -0.3 to 7 V dv/dt Startup time selection pin -0.3 to 7 V Auto Auto retry selection pin -0.3 to 7 V Vg Gate driver pin -0.3 to 65 V TJ Maximum junction temperature (1) 150 °C TSTG Storage temperature range -65 to 150 °C TLEAD Lead temperature (soldering) 10 s 260 °C 1. The thermal limit is set above the maximum thermal rating. It is not recommended to operate the device at temperatures greater than the maximum ratings for extended periods of time. Note: Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Table 3. Recommended operating condition Symbol Parameter Value Unit Operating power supply voltage, steady state 8 to 48 V Maximum power supply voltage, clamping active 52 V RLimit Current sense resistor range (1) 8 to 1000 Ω ID Continuous current 4 A TJ Operating junction temperature -40 to 125 °C VCC 1. Important: The RLimit resistor is mandatory in the application. Very low values of the RLimit or lack of connection of RLimit may lead to malfunction of current limiting circuit and to device damage. Table 4. Thermal data Symbol RthJA RthJC DS12147 - Rev 7 Parameter HTSSOP14 Thermal resistance junction-ambient, 2 layer PCB 140 Thermal resistance junction-ambient, 4 layer PCB 40 Thermal resistance junction-case 4 Unit °C/W °C/W page 4/27 STEF01 Maximum ratings Table 5. ESD performance DS12147 - Rev 7 Symbol Parameter ESD ESD protection voltage Test conditions Value Unit HBM 2 kV CDM 500 V page 5/27 STEF01 Electrical characteristics 4 Electrical characteristics VCC = 24 V, VEN = floating, CI = 10 µF, CO = 47 µF, TJ = 25 °C (unless otherwise specified). Table 6. Electrical characteristics for STEF01 Symbol Parameter Test conditions Min. Typ. Max. Unit Under/over voltage protection Output clamping voltage VClamp VON VHyst Accuracy VCC = 36 V, VClamp = floating 28 V -5 +5 % 52 V 16 V 45 V Output clamping voltage range With external resistor divider on Vclamp pin 10 Under voltage lockout threshold Turn on, voltage going up, UVLO = floating 13 Under voltage lockout range With external resistor divider on UVLO pin 8 UVLO hysteresis 14.5 10 % Power MOSFET RDSon ON resistance VOFF Off state output voltage ID = 1 A (1) 30 50 mΩ -40 °C < TJ < 125 °C (2) 70 VCC = 36 V, VGS = 0, RL = infinite 1 20 mV Current limit IShort Short circuit current limit RLimit = 22 Ω, VOUT = gnd ILim Overload current limit RLimit = 22 Ω, VOUT = VCC - 2 V, VCC > 8 V 1.5 3.2 4 A 4.8 A dv/dt circuit Enable to VOUT = 22 V, No Cdv/dt dv/dt 3 Output voltage ramp time Enable to VOUT = 46 V, VCC = 48 V, VClamp = 52 V, no Cdv/dt Idv/dt ms 3.6 dv/dt source pin current 100 nA Enable/Fault VIL Low level input voltage Output disabled VI(INT) Intermediate level input voltage Thermal fault, output disabled VIH High level input voltage Output enabled 2.8 VI(MAX) High state maximum voltage Pin floating 4.7 IIL Low level input current (sink) VEnable = 0 V 0 0.4 1.4 V V 5 V 5 5.3 V -20 -40 µA 5 Units Maximum fan-out for fault Total number of chips that can be connected to this pin signal for simultaneous shutdown Power Good VD Power Good output threshold VL Power Good output voltage low DS12147 - Rev 7 VCC - VOUT value for Power Good Hysteresis Isink = 6 mA open drain output 1 V 0.1 0.4 V page 6/27 STEF01 Electrical characteristics Symbol Parameter Test conditions Min. Typ. Max. Unit External MOS gate driver Ig Sourcing current Device on 30 µA Rp Strong pull down VEN = 0 V 450 Ω Vg Gate driver voltage Vg-VOUT 8.5 9.5 10.5 V Auto-retry function VAR Autoretry logic level Auto-retry activated Latched protection activated 0.4 1 V Total device consumption IBias Vmin Bias current Device operational 0.4 Thermal shutdown (2) 0.1 Off state (VEN = GND) 0.1 Minimum operating voltage mA 8 V Thermal shutdown TSD Shutdown temperature (2) Hysteresis 175 Only in auto-retry mode 25 °C 1. Pulsed test. 2. Guaranteed by design, but not tested in production. DS12147 - Rev 7 page 7/27 STEF01 Typical application 5 Typical application Figure 3. Application circuit VIN Vcc RL S TEF01 RP G RH C IN Exp.pa d C dv/dt R LIM ILIM PG UVLO VCLAMP dV/dt AUTO EN/Fa ult VOUT VOUT C OUT R1 R2 Vg GND GIPD010220161218MT 5.1 Operating modes 5.1.1 Turn-on and UVLO The device features a programmable UVLO block. If the input voltage exceeds the UVLO ON threshold (VON), the power pass element is turned on and the Enable/Fault pin goes up to the high state. Figure 4. UVLO block simplified diagram shows the simplified diagram of the UVLO circuit. The voltage at the UVLO pin is compared to an internal 1 V reference (0.9 V during turn OFF). The default ON threshold is set by internal divider (RHD, RLD) to 14.5 V; the ID current flowing through the internal divider is set to ~ 3 μA. The UVLO threshold can be modified in accordance with power rail needs by adding the RH-RL resistor divider, as shown in Figure 4. UVLO block simplified diagram. The external divider is in parallel with the internal default one, therefore the threshold can be changed within the 8 V to 45 V range. Figure 4. UVLO block simplified diagram VCC VIN RH R HD UVLO RL IE ID UVLO ON R LD VRe f GND GIPD010220161241MT When the external divider is used, the ratio between external current IE and the internal current ID should be kept as high as possible, to guarantee maximum linearity of the circuit with respect to temperature and process variations. DS12147 - Rev 7 page 8/27 STEF01 Operating modes Setting IE/ID > 10 provides sufficient UVLO linearity, at the same time keeping overall current consumption at acceptable levels. Given the desired VON threshold, for a fixed value of the lower resistor RL, Equation 1 can be used to calculate the upper resistor RH. Equation 1 1 R H = ------------------------------------------------------------------(1 / R L + 1 / 333 ) 1 ------------------------------------------- – -----------------( VO N – 1 ) 4500 (resistor values are expressed in kΩ) Figure 5. UVLO threshold (VON) vs. RH, RL shows the relationship between RH and the UVLO turn ON threshold, for some fixed values of RL. Figure 5. UVLO threshold (VON) vs. RH, RL RL=100k RL=50k 10000 RL=33k RL=20k RL=10k RH [kΩ] 1000 100 10 5 10 15 20 25 30 35 40 45 50 VON [V] The resistor divider approach described above guarantees the best UVLO performance in terms of accuracy and temperature dependance. In order to reduce the application B.O.M., the 1-resistor approach can be used also, at the expenses of overall UVLO circuit accuracy. In this case, the RH resistor can be omitted for VON thresholds higher than 14.5 V, or RL for VON lower than 14.5 V. In any case it is recommended to check that in all operating conditions, the UVLO threshold is never lower than 8 V, in order to guarantee correct operation. After an initial delay time of typically 170 µs, the output voltage is supplied with a slope defined by the internal dv/dt circuitry. If no additional capacitor is connected to the dv/dt pin, the total time from the Enable signal going high and the output voltage reaching the nominal value is around 3 ms. 5.1.2 Normal operating condition The STEF01 E-fuse provides the circuitry on its output with the same voltage shown at its input, with a small voltage fall due to the N-channel MOSFET RDS-on. 5.1.3 Output voltage clamp If the input voltage exceeds the Vclamp value, the internal protection circuit clamps the output voltage to Vclamp. The overvoltage clamp threshold is preset to 28 V if the Vclamp pin is left floating, otherwise it can be externally adjusted in the range of 10 to 52 V by connecting a resistor divider (R1,R2) of appropriate value between the Vclamp pin, VOUT and GND. The setting procedure is similar to that of UVLO, the internal divider current being fixed to 10 µA. Given the desired Vclamp threshold, for a fixed value of the lower resistor R2, Equation 2 can be used to calculate the upper resistor R1 DS12147 - Rev 7 page 9/27 STEF01 Operating modes Equation 2 1 R 1 = -------------------------------------------------------–2 (1 / R 2 + 10 ) 1 ------------------------------------- – ------------( Vc la m p – 1 ) 2700 (resistor values are expressed in kΩ) Figure 6. Clamping voltage (Vclamp) vs. R1, R2 shows the relation between R1 and the clamping voltage, for some fixed values of R2. Figure 6. Clamping voltage (Vclamp) vs. R1, R2 R2=100k 10000 R2=50k R2=20k R2=10k R1 [kΩ] 1000 100 10 5 10 15 20 25 30 35 40 45 50 55 VCLAMP [V] 5.1.4 Current limit The STEF01 embeds an overcurrent sensing circuit, based on an internal N-channel Sense FET with a fixed ratio, used to monitor the output current (Figure 1. Block diagram). The current limiting circuit responds to overcurrent events by reducing the conductivity of the power MOSFET, in order to clamp the output current at a safe value. The overcurrent protection trip-point can be selected externally by means of the limiting resistor RLimit, according to the graphs in Section 5.1.4 Current limit and Figure 25. Current limit vs. Rlimit (zoom). The circuit features two levels of current limitation, each one valid for a certain range of output voltage (VOUT). In case of overload, when the input current surpasses the programmed overload current limit (ILIM), but the output voltage is still higher than 5.5 V (typ.), the device clamps the current to the ILIM value. If case of strong overload or short circuit, when the output voltage decreases to less than 3.5 V, the device enters the foldback current limit, with the current limited to a lower value (ISHORT) that is typically 1.5 A when RLimit = 22 Ω. DS12147 - Rev 7 page 10/27 STEF01 Protection circuits Figure 7. Current limit vs. Rlimit VIN=24V, C IN=C OUT=47µF, IOUT=from 0.5A to 8A, R LIM=from 10Ω to 1kΩ 12 Ilim 10 Is hort Curre nt limit [A] 8 6 4 2 0 10 100 1000 Rlimit [Ω] AMG180720171100MT During startup, the foldback current limit is disabled and the current is limited by the overcurrent protection at the ILIM value. Please refer also to Section 5.4 Maximum load at startup for more details. It is important to note that the RLimit is mandatory for the current limiting circuit to function properly. It is recommended to use RLimit value according to Section 3 and to the package power dissipation. Important: very low values of RLimit or failure to connect it may lead to malfunctioning of the current limiting circuit and to device damage. 5.2 Protection circuits Since the power dissipation can reach remarkable levels during startup into heavy capacitive loads, large load transients and short-circuit during operation at high voltage, the STEF01 is protected by means of two circuits: the absolute thermal protection and the maximum power dissipation protection. 5.2.1 Thermal protection The thermal protection is a standard thermal shutdown feature, which acts when the die temperature exceeds the absolute shutdown threshold, set typically to 175 °C. The behavior of the STEF01 at thermal protection intervention can be changed by the user through the external Auto pin. This pin is internally pulled up. When the Auto pin is left floating or connected to a voltage higher than 1 V, the thermal protection works as latched. If the device temperature exceeds the thermal shutdown threshold, the thermal shutdown circuitry turns the power MOSFET off, disconnecting the load. The EN/Fault pin of the device will be automatically set at an intermediate voltage, typically 1.4 V, in order to signal the overtemperature event. The E-fuse can be reset either by cycling the supply voltage or by pulling down the EN pin below the VIL threshold and then releasing it. When the AUTO pin is connected to GND or to a voltage lower than 0.4 V, the thermal protection works as auto-retry. Once the thermal protection threshold is reached, the power is turned off and remains in an off state until the die temperature drops below the hysteresis value. Once this occurs, the internal auto-retry circuit initiates a new startup cycle, with controlled dv/dt. During the shutdown period, the EN/Fault pin of the device will be automatically set to 0 V. 5.2.2 Maximum dissipated power protection Besides the standard thermal shutdown described in Section 5.2.1 Thermal protection, which acts when the die temperature surpasses the absolute shutdown threshold, the STEF01 is equipped with advanced thermal protection, which limits the thermal power dissipated into the device. When the power dissipation is higher than the internal limit, the power transistor is turned off. The power protection always acts in auto-retry mode, regardless of the Auto pin status. Its intervention is signaled on the EN/FAULT pin with a LOW logic state. If the fault persists, the die temperature may reach the thermal protection limit. If this happens, the device behavior is the one fixed by the user through the Auto pin signal. The maximum dissipated power protection is able to protect the device from very fast overheating events, such as those caused by a short circuit on the output during operation. DS12147 - Rev 7 page 11/27 STEF01 Soft start function 5.3 Soft start function The inrush current profile is controlled through a dedicated soft-start circuit. The startup time is set by default at 3 ms (typ.) and it can be prolonged by connecting a capacitor between the Cdv/dt pin and GND. Figure 8. Startup time illustrates the turn-on sequence. The turn-on time is defined as the time interval tΟΝ between assertion of the enable signal and the Vout reaching the (VOUT(NOM)-2 V) voltage. The turn-on time is a function of the Cdv/dt capacitor, the input voltage VCC and the clamping voltage VClamp. Given the Cdv/dt external capacitor value, the turn-on time can be estimated using Equation 3 and the graph in Figure 9. Startup time vs. CdV/dt, valid for normal operating conditions (VCC < VClamp). In case the startup occurs with power supply voltage higher than the clamping voltage (VCC > VClamp), the total startup time will be longer. The equation is meant as a theoretical aid in choosing the Cdv/dt capacitor, and does not take into account the capacitor tolerance, temperature and process variations. Equation 3 VC C ( 300 + C d vd t ) t O N = 0.952 ⋅ ------------------- ⋅ ----------------------------------- + t d e la y VC la m p 113000 where time is expressed in [s] and the capacitor in [pF]; tdelay ~ 170 µs, is the initial delay time. Figure 9. Startup time vs. CdV/dt Figure 8. Startup time 1000 Vcc=24V Vcc=48V Vcla mp 100 VIN - 2V EN/FAULT ra mp-up time – VIN>VCla mp de la y time (tde la y) ra mp-up time – VIN