STEF05DPUR

STEF05D Electronic fuse for 5 V line Datasheet - production data  Hard disk and SSD arrays  Set-top boxes  DVD and Blu-ray disc drivers Description The STEF05D is an integrated electronic fuse optimized for monitoring output current and input voltage. Connected in series to a 5 V rail, it is capable of protecting the electronic circuitry on its output from overcurrent and overvoltage. The device has a controlled delay and turn-on time. When an overload condition occurs, the STEF05D limits the output current to a predefined safe value. If the anomalous overload condition. persists, it goes into an open state, disconnecting the load from the power supply. If a continuous short-circuit is present on the board, when power is re-applied the E-fuse initially limits the output current to a safe value, and then again goes into an open state. DFN10 (3 x 3 mm) Features  Continuous current typ: 3.6 A  N-channel on-resistance typ: 40 m  Enable/fault functions  Output clamp voltage typ: 6.65 V The device is equipped with a thermal protection circuit. The intervention of the thermal protection is signal led to the board monitoring circuits through a signal on the Fault pin.  Undervoltage lockout  Short-circuit limit  Overload current limit  Controlled output voltage ramp  Thermal latch typ: 165 °C  Uses tiny capacitors  Operating junction temp. - 40 °C to 125 °C  Available in DFN10 (3 x 3 mm). Applications Unlike mechanical fuses, which must be physically replaced after a single event, the Efuse does not degrade in its performance after short-circuit/thermal protection interventions and it is reset either by recycling the supply voltage or using the Enable pin. The companion chip for 12 V power rails is also available with part number STEF12.  Hard disk drives  Solid state drives (SSD) Table 1. Device summary Order code Package Packaging STEF05DPUR DFN10 (3 x 3 mm) Tape and reel May 2020 This is information on a product in full production. DocID024394 Rev 2 1/19 www.st.com 19 Contents STEF05D Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 Typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1.1 Turn-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1.2 Normal operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.1.3 Output voltage clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.1.4 Current limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.1.5 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.2 RLimit calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.3 Cdv/dt calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.4 Enable/fault pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2/19 DocID024394 Rev 2 STEF05D 1 Block diagram Block diagram Figure 1. Device block diagram AM09891v1 DocID024394 Rev 2 3/19 Pin configuration 2 STEF05D Pin configuration Figure 2. Pin configuration (top view) Source Source Source Source Source GND dv/dt En/fault I-Limit N/C VCC AM09867v1 Table 2. Pin description Pin N° Symbol 1 to 5 VOUT/Source 6 NC 7 I-Limit A resistor between this pin and the Source pin sets the overload and shortcircuit current limit levels. En/Fault The enable/fault pin is a tri-state, bi-directional interface. During normal operation the pin must be left floating, or it can be used to disable the output of the device by pulling it to Ground using an open drain or open collector device. If a thermal fault occurs, the voltage on this pin will go to an intermediate state to signal a monitor circuit that the device is in thermal shutdown. It can be connected to another device of this family to cause a simultaneous shutdown during thermal events. 9 dv/dt The internal dv/dt circuit controls the slew rate of the output voltage at turnon. The internal capacitor allows a ramp-up time of around 1ms. An external capacitor can be added to this pin to increase the ramp time. If an additional capacitor is not required, this pin should be left open. 10 GND Ground Pin 11 VCC Exposed pad. Positive input voltage must be connected to VCC. 8 4/19 Note Connected to the Source of the internal power MOSFET and to the output terminal of the fuse Not connected DocID024394 Rev 2 STEF05D 3 Maximum ratings Maximum ratings Table 3. Absolute maximum ratings Symbol VCC Parameter Value Positive power supply voltage (steady state) -0.3 to 10 Positive power supply voltage (max 100 ms) -0.3 to 15 VOUT/source (max 100 ms) I-Limit (max 100 ms) En/Fault dv/dt range(1) TOP Operating junction temperature TSTG Storage temperature range TLEAD Lead temperature (Soldering) 10 sec Unit V -0.3 to Vcc+0.3 V -0.3 to 15 V -0.3 to 7 V -0.3 to 7 V -40 to 125 °C -65 to 150 °C 260 °C 1. The thermal limit is set above the maximum thermal rating. It is not recommended to operate the device at temperatures greater than the maximum ratings for extended periods of time. Note: Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Table 4. Thermal data Symbol Parameter Value Unit RthJA Thermal resistance junction-ambient 52.7 °C/W RthJC Thermal resistance junction-case 17.4 °C/W Test conditions Value Unit HBM 2 KV MM 150 V CDM 500 V Table 5. ESD performances Symbol ESD Parameter ESD Protection DocID024394 Rev 2 5/19 Electrical characteristics 4 STEF05D Electrical characteristics VCC = 5 V, VEN = 3.3 V, CI = 10 µF, CO = 47 µF, TJ = 25 °C, unless otherwise specified Table 6. Electrical characteristics for STEF05D Symbol Parameter Test conditions Min. Typ. Max. Unit Under/Overvoltage Protection VClamp Output clamping voltage VCC = 10 V 5.95 6.65 7.7 V VUVLO Undervoltage lockout Turn-on, voltage going up 3.2 3.6 4.3 V VHyst UVLO Hysteresis 0.40 V Power MOSFET tdly Delay time Enabling of chip to ID = 100 mA with a 1 A resistive load 200 TJ = 25 °C 40 RDSon ON resistance(1) VOFF Off state output voltage VCC = 10 V, VGS = 0, RLimit = infinite 50 Continuous current 0.5 inch² pad (2), TA = 25 °C 3.6 Minimum copper, TA = 80 °C 1.7 ID µs 60 70 TJ = 125 °C (2) 200 m mV A Current Limit IShort ILim Short-circuit current limit RLimit = 11  Overload current limit RLimit = 11  3.1 4.1 5.1 A 4 A 0.8 ms dv/dt Circuit dv/dt Output voltage ramp time Enable to VOUT=4.7V, No Cdv/dt Enable/Fault Low level input voltage(2) Output Disabled 0.35 0.58 0.81 V VI(INT) Intermediate level input voltage(2) Thermal Fault, Output Disabled 0.82 1.4 1.95 V VIH High level input voltage Output Enabled 1.96 2.64 3.3 V 3.4 4.3 5.4 V -10 -30 µA VIL VI(MAX) High state maximum voltage IIL Low level input current (sink) VEnable = 0 V II High level leakage current for external switch VEnable = 3.3 V 1 µA Maximum fan-out for fault signal Total numbers of chips that can be connected to this pin for simultaneous shutdown 3 Units 6/19 DocID024394 Rev 2 STEF05D Electrical characteristics Table 6. Electrical characteristics for STEF05D Symbol Parameter Test conditions Min. Typ. Max. Device operational 0.5 2 Thermal Shutdown 1 Unit Total Device IBias Vmin Bias current Minimum operating voltage 3.1 mA V Thermal Latch TSD Shutdown temperature(2) 165 °C 1. Pulse test: Pulse width = 300 µs, Duty cycle = 2% 2. Limits in temperature are guaranteed by design, but not tested in production DocID024394 Rev 2 7/19 Typical application 5 STEF05D Typical application Figure 3. Application circuit AM09868v1 Figure 4. Typical HDD application circuit AM09869v1 5.1 Operating modes 5.1.1 Turn-on When the input voltage is applied, the Enable/Fault pin goes up to the high state, enabling the internal control circuitry. After an initial delay time of typically 200 µs, the output voltage is supplied with a slope defined by the internal dv/dt circuitry. If no additional capacitor is connected to dv/dt pin, the total time from the Enable signal going high and the output voltage reaching the nominal value is around 1 ms (refer to Figure 5 and Figure 7). 8/19 DocID024394 Rev 2 STEF05D 5.1.2 Typical application Normal operating condition The STEF05D E-fuse behaves like a mechanical fuse, buffering the circuitry on its output with the same voltage shown at its input, with a small voltage fall due to the N-channel MOSFET RDSOn. 5.1.3 Output voltage clamp This internal protection circuit clamps the output voltage to a maximum safe value, typically 6.65V, if the input voltage exceeds this threshold. 5.1.4 Current limiting When an overload event occurs, the current limiting circuit reduces the conductivity of the power MOSFET, in order to clamp the output current at the value selected externally by means of the limiting resistor RLimit (Figure 3). 5.1.5 Thermal shutdown If the device temperature exceeds the thermal latch threshold, typically 165°C, the thermal shutdown circuitry turns the power MOSFET off, thus disconnecting the load. The EN/Fault pin of the device will automatically be set at an intermediate voltage, in order to signal the overtemperature event. From this condition the E-fuse can be reset either by cycling the supply voltage or by pulling down the EN pin below the Vil threshold, and then releasing it. 5.2 RLimit calculation As shown in Figure 3, the device uses an internal N-channel sense FET with a fixed ratio, to monitor the output current and limit it at the level set by the user. The RLimit value for achieving the requested current limitation can be estimated by using the following theoretical formula, together with the graph in Figure 13: Equation 1 42 R Limit = ---------------Ishort 5.3 Cdv/dt calculation Connecting a capacitor between the Cdv/dt pin and GND will allow the modification of the output voltage ramp time. Given the desired time interval t during which the output voltage goes from zero to his maximum value, the capacitance to be added on Cdv/dt pin can be calculated using the following theoretical formula: DocID024394 Rev 2 9/19 Typical application STEF05D Equation 2 –9 C dvdt = 36  10 t – 30x10 – 12 Where Cdv/dt is expressed in Farad, and the time t in seconds. Figure 5 shows a graphical explanation of delay time and ramp-up time. Figure 5. Delay time and VOUT ramp-up time AM09870v1 6 VOUT 5 V 4 delay time ramp-up time EN/Fault 3 2 1 0 Time 5.4 Enable/fault pin The Enable/Fault pin has the dual function of controlling the output of the device and, at the same time, of providing information about the device status to the application. When it is used, it should be connected to an external open-drain or open-collector device. In this case, when it is pulled at low logic level, it turns the output of the E-Fuse off. If this pin is left floating, since it has internal pull-up circuitry, the output of the E-Fuse is kept ON in normal operating conditions. In case of thermal fault, the pin is pulled to an intermediate state (Figure 6). This signal can be provided to a monitor circuit, informing it that a thermal shutdown has occurred, or it can be directly connected to the Enable/Fault pins of other STEFxx devices on the same application in order to achieve a simultaneous enable/disable feature. When a thermal fault occurs, the device can be reset either by cycling the supply voltage or by pulling down the Enable pin below the Vil threshold and then releasing it. 10/19 DocID024394 Rev 2 STEF05D Typical application Figure 6. Enable/fault pin status 5 Normal operating condition EN/Fault voltage [V] 4 3 2 Thermal fault condition 1 Off/Reset 0 time DocID024394 Rev 2 AM09871v1 11/19 Typical performance characteristics 6 STEF05D Typical performance characteristics The following plots are referred to the typical application circuit and, unless otherwise noted, at TA = 25°C. Figure 7. VOUT ramp-up vs. EN/fault Figure 8. Startup vs. VCC VCC VOUT VCC VOUT EN/FLT EN/FLT Figure 9. Startup @ short-circuit Figure 10. Startup @ heavy load EN/FLT EN/FLT VOUT Iin Iin VCC VCC VOUT Figure 11. Startup vs. EN/fault Figure 12. Clamp voltage EN/FLT VCC VCC VOUT VOUT 12/19 DocID024394 Rev 2 STEF05D Typical performance characteristics Figure 13. Current limit and short circuit current vs. Rlimit Figure 14. RDSON vs. temperature AM09877v2 80  V CC = 5 V ,/,0 ,6+257  70  60 R DS ON (m Ω) , OLP, VKRUW >$@     50 40   30                      20 5 /,0,7 >Ÿ@ -40 -25 0 25 55 85 125 150 Temperature (°C) DocID024394 Rev 2 13/19 Package mechanical data 7 STEF05D Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Table 7. DFN10L (3 x 3 mm.) mechanical data mm. Dim. A Min. Typ. Max. 0.80 0.90 1.00 0.02 0.05 0.65 0.80 A1 A2 0.55 A3 0.20 b 0.18 0.25 0.30 D 2.85 3.00 3.15 D2 2.20 E 2.85 E2 1.40 3.00 0.230 E4 0.365 e 0.50 0.30 ddd 3.15 1.75 E3 L 14/19 2.70 0.40 0.50 0.08 DocID024394 Rev 2 STEF05D Package mechanical data Figure 15. DFN10L package outline 7426335_H DocID024394 Rev 2 15/19 Package mechanical data STEF05D Tape and reel QFNxx/DFNxx (3x3 mm) mechanical data mm. inch. Dim. Min. Typ. A Min. Typ. 330 13.2 12.8 D 20.2 0.795 N 60 2.362 0.504 0.519 18.4 0.724 Ao 3.3 0.130 Bo 3.3 0.130 Ko 1.1 0.043 Po 4 0.157 P 8 0.315 DocID024394 Rev 2 Max. 12.992 C T 16/19 Max. STEF05D Package mechanical data Figure 16. DFN10L footprint - recommended data (dimensions in mm.) 7426335_H DocID024394 Rev 2 17/19 Revision history 8 STEF05D Revision history Table 8. Document revision history 18/19 Date Revision Changes 19-Mar-2013 1 Initial release. 22-May-2020 2 Datasheet promoted from preliminary data to production data. Updated Figure 13. DocID024394 Rev 2 STEF05D IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. 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Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2020 STMicroelectronics – All rights reserved DocID024394 Rev 2 19/19