STEF05LAPUR

STEF05L Electronic fuse for 5 V line Features • • • • • • • • • • • • • Continuous current typ.: 3.6 A (DFN), 2.5 A (Flip Chip) N-channel on resistance (typ): 40 mΩ (DFN), 25 mΩ (Flip Chip) Enable/Fault functions Output clamp voltage (typ.): 6.1 V Undervoltage lockout Short-circuit limit Overload current limit Controlled output voltage ramp Thermal latch (typ): 160 °C Uses tiny capacitors Latching and auto-retry versions Operative junction temp. - 40 °C to 125 °C Available in DFN10 (3 x 3 mm) and Flip Chip 9 bumps Applications Maturity status link STEF05L • • • • • Hard disk drives Solid state drives (SSD) Hard disk and SSD arrays Computer DVD and Blu-Ray disc drivers Description The STEF05L is an integrated electronic fuse optimized for monitoring output current and the input voltage. Connected in series to the 5 V rail, it is able to protect the electronic circuitry on its output from overcurrent and overvoltage. The STEF05L has controlled delay and turn-on time. When an overload condition occurs, the device limits the output current to a predefined safe value. If the anomalous overload condition persists, it goes into an open state, disconnecting the load from the power supply. If a continuous short-circuit is present on the board, when the power is re-applied the eFuse initially limits the output current to a safe value and then goes again into the open state. The voltage clamping circuit prevents the output voltage from exceeding a fixed value, if the input voltage goes beyond this threshold. The device is equipped with a thermal protection circuit. Intervention of thermal protection is signaled to the board-monitoring circuits through an appropriate signal on the Fault pin. Unlike mechanical fuses, which must be physically replaced after a single event, the eFuse does not degrade in its performances following short-circuit/thermal protection intervention and is reset either by re-cycling the supply voltage or using the appropriate Enable pin. The STEF05L is also available in an autoretry version; in case of thermal fault it automatically attempts to re-apply power to the load when the die temperature returns to a safe value. DS11527 - Rev 2 - December 2020 For further information contact your local STMicroelectronics sales office. www.st.com STEF05L Device block diagram 1 Device block diagram Figure 1. Block diagram DS11527 - Rev 2 page 2/25 STEF05L Pin configuration 2 Pin configuration Figure 2. Pin configuration A 1 10 2 9 3 exp pad 8 4 7 5 6 B C 3 2 1 DFN10 (3 x 3mm) (top view) Flip Chip 9 (marking view) GIPD040220161119MT Table 1. Pin description Pin n° Pin n° Symbol DFN10 (3 x 3 mm) Flip Chip 9 1, 2, 3, 4, 5 C1, C2, C3 VOUT/source 6 N.C. I-lim - 7 A1 I-lim + 8 A2 En/Fault Note Connected to the source of the internal power MOSFET and to the output terminal of the eFuse. A resistor between these two pins sets the overload and short-circuit current limit levels. On the Flip Chip the resistor must be connected between the I-Lim+ and Source pins. The Enable/Fault pin is a tri-state, bi-directional interface. During normal operation the pin must be left floating, or it can be used to disable the output of the device by pulling it to ground using an open drain or open collector device. If a thermal fault occurs, the voltage on this pin goes into an intermediate state to signal a monitor circuit that the device is in thermal shutdown. It can be connected to another device of this family to cause a simultaneous shutdown during thermal events. 9 N.C. dv/dt The internal dv/dt circuit controls the slew rate of the output voltage at turn-on. The internal capacitor allows a ramp-up time of around 1.4 ms. An external capacitor can be added to this pin to increase the ramp time. If an additional capacitor is not required, this pin should be left open. This feature is not available on the Flip Chip version. 10 A3 GND Ground pin. Exposed pad B1, B2, B3 VCC DS11527 - Rev 2 Exposed pad. Positive input voltage must be connected to VCC. page 3/25 STEF05L Maximum ratings 3 Maximum ratings Table 2. Absolute maximum ratings Symbol VCC VOUT/Source I-Lim+/I-LimEn/Fault Parameter Value Unit Positive power supply voltage -0.3 to 10 V VOUT pin voltage -0.3 to 7 VOUT pin voltage (100 ms) V - 0.3 to VCC + 0.3 Current limit pin voltage -0.3 to 7 V - 0.3 to VCC + 0.3 Current limit pin voltage (100 ms) Enable/Fault pin voltage -0.3 to 4.6 V dv/dt dv/dt pin voltage -0.3 to 4.6 V TOP Operating junction temperature range (1) - 40 to 125 °C TSTG Storage temperature range - 65 to 150 °C TLEAD Lead temperature (soldering) 10 sec 260 °C 1. The thermal limit is set above the maximum thermal rating. It is not recommended to operate the device at temperatures greater than the maximum ratings for extended periods of time. Note: Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Table 3. Recommended operating condition Symbol VCC RLimit Parameter Positive power supply voltage Value Unit 4.5 to 8 V Current sense resistor range, STEF05L, STEF05LA 10 to 120 Current limitation resistor range, STEF05LJ, STEF05LAJ 15 to 120 Ω Cdv/dt Soft-start capacitor range 0 to 1 nF VEN Enable/Fault pin voltage 0 to 3.6 V Table 4. Thermal data Symbol RthJA RthJC Parameter Value Thermal resistance junction-ambient, DFN10 (3 x 3 mm) 70 Thermal resistance junction-ambient, Flip Chip 9 90 Thermal resistance junction-case, DFN10 (3 x 3 mm) 34 Unit °C/W Table 5. ESD performance Symbol ESD DS11527 - Rev 2 Parameter ESD protection Test conditions Value Unit HBM 4 kV MM 400 V CDM DFN10 (3 x 3 mm) 500 V CDM (Flip Chip 9) 250 V page 4/25 STEF05L Electrical characteristics 4 Electrical characteristics VCC = 5 V, CI = 10 μF, CO =10 μF, TJ = 25 °C (unless otherwise specified). Table 6. Electrical characteristics Symbol Parameter Test conditions Min. Typ. Max. Unit Under/over voltage protection VClamp Output clamping voltage VCC = 8 V 5.5 6.1 6.8 V VUVLO Under voltage lockout Turn-on, voltage increasing 3.1 3.4 4.0 V VHyst UVLO hysteresis 0.1 V Enabling of chip to VOUT = 10 % of nominal value 500 µs IOUT = 500 mA, TJ = 25 °C 40 Power MOSFET tdly Delay time ON resistance (DFN package) (1) RDSon ON resistance (Flip Chip package) (1) VOFF ID Off state output voltage Continuous current IOUT= 500 mA, -40 °C < TJ < 125 °C 60 70 IOUT = 500 mA, TJ = 25 °C 30 50 IOUT = 500 mA, -40 °C < TJ < 125 °C 70 VEN = GND, RL = infinite 100 DFN package 3.6 Flip Chip package 2.5 mΩ mΩ mV A Current limit IShort ILim Short-circuit current limit RLimit = 24 Ω, DFN package 0.8 1.2 1.6 RLimit = 24 Ω, Flip Chip package 1.1 1.5 1.9 Overload current limit RLimit = 24 Ω (2) Output voltage ramp time VOUT = 10 % to 90 % of nominal voltage, No Cdv/dt Low level input voltage Output disabled (2) Intermediate level input voltage Thermal fault, output disabled (2) 0.8 High level input voltage Output enabled 2.5 2.5 A A dv/dt circuit dv/dt 0.8 1.4 2.5 ms 0.5 V 2 V Enable/Fault VIL VI(INT) VIH VI(MAX) High state maximum voltage IIL Low level input current (sink) VEnable = GND Maximum fan-out for fault signal Total number of chips that can be connected to this pin for simultaneous shutdown (2) 1.4 V 3.25 -28 V -50 µA 3 Units Total device IBias DS11527 - Rev 2 Bias current Device operational 0.7 Thermal shutdown (only on latching versions) (2) 0.5 Device disabled (VEN = GND) 0.35 2 mA page 5/25 STEF05L Electrical characteristics Symbol Parameter Test conditions Min. Typ. Max. Unit Thermal latch TSD Shutdown temperature (2) Hysteresis Only on auto-retry versions (2) 160 25 °C 1. Pulse test. 2. Guaranteed by design, but not tested in production. DS11527 - Rev 2 page 6/25 STEF05L Typical application 5 Typical application Figure 3. Application circuit, STEF05L and STEF05LA (DFN10 (3 x3 mm) package) GIPD040220161423MT Figure 4. Application circuit with Kelvin current sensing, STEF05LJ and STEF05LAJ (Flip-Chip 9 bump package) GIPD040220161425MT 5.1 Operating modes 5.1.1 Turn-on When the input voltage is applied, the Enable/Fault pin goes up to the high state, enabling the internal control circuitry. After an initial delay time of typically 500 ms, the output voltage is supplied with a slope defined by the internal dv/dt circuitry. If no additional capacitor is connected to dv/dt pin, the total time from the Enable signal going high and the output voltage reaching the nominal value is around 1.6 ms (refer to Figure 5. Delay time and VOUT rise time, and Figure 15. VOUT turn-on vs enable). 5.1.2 Normal operating condition The STEF05L eFuse behaves like a mechanical fuse, buffering the circuitry on its output with the same voltage shown at its input, with a small voltage fall due to the N-Channel MOSFET RDSOn. DS11527 - Rev 2 page 7/25 STEF05L RLimit calculation 5.1.3 Output voltage clamp This internal protection circuit clamps the output voltage to a maximum safe value, typically 6.1 V, if the input voltage exceeds this threshold. 5.1.4 Current limiting When an overload event occurs, the current limiting circuit reduces the conductivity of the power MOSFET, in order to clamp the output current at the value selected externally by means of the limiting resistor RLimit (Figure 3. Application circuit, STEF05L and STEF05LA (DFN10 (3 x3 mm) package)). 5.1.5 Thermal shutdown and auto-retry function If the device temperature exceeds the thermal latch threshold, typically 160 °C, the thermal shutdown circuitry turns the power MOSFET off, thus disconnecting the load. The EN/Fault pin of the device is automatically set to an intermediate voltage, in order to signal the overtemperature event. The STEF05L latch version can be reset from this condition either by cycling the supply voltage or by pulling down the EN pin below the Vil threshold and then releasing it. On the STEF05LA auto-retry version, the power MOSFET will remain in an OFF state until the die temperature drops below the hysteresis value. Once this happens, the internal autoretry circuit attempts to reset the device, pulling up the EN/Fault pin to the operative value. 5.2 RLimit calculation As shown in Figure 1. Block diagram the device uses an internal N-Channel Sense FET with a fixed ratio, to monitor the output current and limit it at the level set by the user. The RLimit value for achieving the requested current limitation can be estimated by using the “current limit vs RLimit”, graph in Figure 12. Current limit vs RLimit (IOUT ramp). The device has two levels of current limitation, depending on the load condition. The short-circuit current limit (IShort) is the current level that is imposed when the output voltage decreases sharply, as in the case of a short-circuit on the output. The overload current limit (ILim), also described as “current limit trip-point”, represents the current level that is recognized by the device as an overload condition. Following this, the current limit trip point is reached the device enters into current limitation, and the current to the load is limited to the IShort value, which is generally lower than the trip-point value. The overload current limit (ILim) is dependent on the device reaction time, so it is influenced by the load current slew-rate. The faster the current increase, the higher the current limit trip point. 5.3 Cdv/dt calculation The device includes a rise-time control circuit, allowing the soft-start during turn-on and Hotplug of the equipment. The pre-programmed rise time, defined as the time interval during which the output voltage goes from 10 % to 90 % of the nominal voltage, is typically 1.4 ms. The STEF05L and STEF05LA in DFN10 package feature a user-programmable output voltage ramp-up time; by connecting a capacitor between the Cdv/dt pin and GND, modification of the output voltage ramp-up time is possible. The capacitance to be added on the Cdv/dt pin can be selected using the following table. Table 7. Typical rise time values vs dv/dt capacitor Cdv/dt Rise time [ms] (1) None 100 pF 470 pF 1 nF 1.4 2.8 8 16 1. VCC = 5 V, CIN = 10 μF, COUT = 10 μF, RLIMIT = 24 Ω, IOUT = 1 A. DS11527 - Rev 2 page 8/25 STEF05L Enable-Fault pin Figure 5. Delay time and VOUT rise time GIPD080220161046MT 5.4 Enable-Fault pin The Enable/Fault pin has the dual function of controlling the output of the device and, at the same time, of providing information about the device status to the application. It can be connected to an external open-drain or open-collector device. In this case, when it is pulled at low logic level, it will turn the output of the eFuse off. If this pin is left floating, since it has internal pull-up circuitry, the output of the eFuse is kept ON in normal operating conditions. This pin should never be biased to a voltage higher than 3.6 V. In case of thermal fault, the pin is pulled to an intermediate state (Figure 6. Enable/Fault pin status). This signal can be provided to a monitor circuit, signaling that a thermal shutdown has occurred, or it can be directly connected to the Enable/Fault pins of other STEFxx devices on the same application, in order to achieve a simultaneous enable/disable feature. When a thermal fault occurs, the device can be reset either by cycling the supply voltage or by pulling down the Enable pin below the Vil threshold and then releasing it. DS11527 - Rev 2 page 9/25 STEF05L Enable-Fault pin Figure 6. Enable/Fault pin status GIPD080220161207MT DS11527 - Rev 2 page 10/25 STEF05L Typical performance characteristics 6 Typical performance characteristics The following plots are referred to the typical application circuit and, unless otherwise noted, at TA = 25 °C. Figure 8. Short-circuit current vs temperature Figure 7. Clamping voltage vs temperature 3 8 Vcc = 5 V, R - limit = 24 Ω, flip-chip pa cka ge VCC = 8 V 7 2.5 6 2 Is h o rt [A] 5 4 3 1.5 1 2 0.5 1 0 0 -40 -25 0 25 55 85 125 -40 -25 0 25 55 GIPD190220160931MT Figure 10. Bias current vs temperature (device disabled) 2 2 Vcc = 5 V, VEN = floating 1.8 1.4 1.2 1.2 Ibias [ mA] 1.6 1.4 Ibias [mA] 1.6 1 Vcc = 5 V, VEN = GND 1 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 0 0 -40 -25 0 25 55 85 125 GIPD190220160933MT DS11527 - Rev 2 125 GIPD190220160932MT Figure 9. Bias current vs temperature (device operational) 1.8 85 -40 -25 0 25 55 85 125 GIPD190220160934MT page 11/25 STEF05L Typical performance characteristics Figure 12. Current limit vs RLimit (IOUT ramp) Figure 11. ON resistance vs temperature 70 6 Vcc = 5 V, DFN10 package 60 Ishort 5 Ilimit Limit & short current (A) RDS -ON [mΩ ] 50 40 Iout 500 mA 30 Iout 1 A Iout 2 A 20 Iout 4 A 10 0 -40 -20 0 20 40 60 80 100 120 140 4 3 2 1 0 0 20 40 60 80 100 120 140 External sensing resistor (Ω) GIPD190220160935MT DS11527 - Rev 2 GIPD190220160936MT Figure 13. VOUT ramp-up vs enable (NO Cdvdt) Figure 14. VOUT ramp-up vs enable (Cdvdt = 470 pF) Figure 15. VOUT turn-on vs enable Figure 16. VOUT turn-off vs enable page 12/25 STEF05L Typical performance characteristics DS11527 - Rev 2 Figure 17. Startup (slow rising) Figure 18. Startup and voltage clamp Figure 19. Startup into output short-circuit Figure 20. Voltage clamp page 13/25 STEF05L Package information 7 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. DS11527 - Rev 2 page 14/25 STEF05L DFN10 (3x3 mm) package information 7.1 DFN10 (3x3 mm) package information Figure 21. DFN10 (3x3 mm) package outline 7426335_L DS11527 - Rev 2 page 15/25 STEF05L DFN10 (3x3 mm) package information Table 8. DFN10 (3x3 mm) mechanical data Dim. mm Min. Typ. Max. 0.80 0.90 1.00 A1 0.02 00.5 A2 0.70 A3 0.20 A b 0.18 0.23 0.30 D 2.85 3.00 3.15 D2 2.23 2.38 2.50 E 2.85 3.00 3.15 E2 1.49 1.64 1.75 E3 0.230 E4 0.365 e L 0.50 0.30 0.40 ddd 0.50 0.08 Figure 22. DFN10 (3x3 mm) recommended footprint 7426335_L DS11527 - Rev 2 page 16/25 STEF05L QFNxx/DFNxx (3 x 3 mm) package information 7.2 QFNxx/DFNxx (3 x 3 mm) package information Figure 23. DFN10 (3x3 mm) tape and reel outline Table 9. DFN10 (3x3 mm) tape and reel mechanical data Dim. mm Min. Typ. A 330 C 12.8 D 20.2 N 60 13.2 T DS11527 - Rev 2 Max. 18.4 Ao 3.3 Bo 3.3 Ko 1.1 Po 4 P 8 page 17/25 STEF05L Flip Chip 9 package information 7.3 Flip Chip 9 package information Figure 24. Flip Chip 9 package outline 7504895_M Table 10. Flip Chip 9 mechanical data Dim. DS11527 - Rev 2 mm Min. Typ. Max. A 0.50 0.55 0.60 A1 0.17 0.20 0.23 A2 0.33 0.35 0.37 b 0.23 0.25 0.29 D 1.16 1.19 1.22 page 18/25 STEF05L Flip Chip 9 package information Dim. mm Min. Typ. D1 E Max. 0.8 1.16 1.19 E1 0.8 e 0.40 f 0.195 ccc 0.075 1.22 Figure 25. Flip Chip 9 recommended footprint 0.8 0.4 0.4 0.8 C B A 3 2 1 Ø 0.22 Grid placemente area DS11527 - Rev 2 page 19/25 STEF05L Ordering information 8 Ordering information Table 11. Order code DS11527 - Rev 2 Tape and reel Package Version Marking STEF05LPUR DFN10 (3 x 3 mm) Latch EF05L STEF05LJR Flip Chip 9 Latch 5L STEF05LAPUR DFN10 (3 x 3 mm) Auto-retry EF05LA STEF05LAJR Flip Chip 9 Auto-retry 5A page 20/25 STEF05L Revision history Table 12. Document revision history DS11527 - Rev 2 Date Revision Changes 04-Nov-2016 1 Initial release 15-Dec-2020 2 Updated Figure 9 and Figure 10 page 21/25 STEF05L Contents Contents 1 Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 4 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 Typical application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5.1 Operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5.1.1 Turn-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5.1.2 Normal operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5.1.3 Output voltage clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1.4 Current Limiting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1.5 Thermal shutdown and auto-retry function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.2 RLimit calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.3 Cdv/dt calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.4 Enable-Fault pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 7 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 8 7.1 DFN10 (3 x 3 mm) package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.2 QFNxx/DFNxx(3 x 3 mm) packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.3 Flip Chip 9 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 List of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 List of figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 DS11527 - Rev 2 page 22/25 STEF05L List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Pin description. . . . . . . . . . . . . . . . . . . . . . . . Absolute maximum ratings . . . . . . . . . . . . . . . Recommended operating condition . . . . . . . . . Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . ESD performance . . . . . . . . . . . . . . . . . . . . . Electrical characteristics . . . . . . . . . . . . . . . . . Typical rise time values vs dv/dt capacitor . . . . . DFN10 (3x3 mm) mechanical data . . . . . . . . . . DFN10 (3x3 mm) tape and reel mechanical data Flip Chip 9 mechanical data . . . . . . . . . . . . . . Order code . . . . . . . . . . . . . . . . . . . . . . . . . . Document revision history . . . . . . . . . . . . . . . . DS11527 - Rev 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 . 4 . 4 . 4 . 4 . 5 . 8 16 17 18 20 21 page 23/25 STEF05L List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. DS11527 - Rev 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application circuit, STEF05L and STEF05LA (DFN10 (3 x3 mm) package) . . . . . . . . . . . . . . . . . . . . . Application circuit with Kelvin current sensing, STEF05LJ and STEF05LAJ (Flip-Chip 9 bump package) Delay time and VOUT rise time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enable/Fault pin status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clamping voltage vs temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Short-circuit current vs temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bias current vs temperature (device operational). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bias current vs temperature (device disabled). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ON resistance vs temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current limit vs RLimit (IOUT ramp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VOUT ramp-up vs enable (NO Cdvdt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VOUT ramp-up vs enable (Cdvdt = 470 pF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VOUT turn-on vs enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VOUT turn-off vs enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Startup (slow rising) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Startup and voltage clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Startup into output short-circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage clamp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DFN10 (3x3 mm) package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DFN10 (3x3 mm) recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DFN10 (3x3 mm) tape and reel outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flip Chip 9 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flip Chip 9 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 . 3 . 7 . 7 . 9 10 11 11 11 11 12 12 12 12 12 12 13 13 13 13 15 16 17 18 19 page 24/25 STEF05L IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2020 STMicroelectronics – All rights reserved DS11527 - Rev 2 page 25/25