STEF12EPUR

STEF12 Datasheet Electronic fuse for 12 V line Features DFN10L (3x3 mm) Maturity status link STEF12 • • • • • • • • • • • • Continuous current (typ): 3.6 A N-channel on-resistance (typ): 53 mΩ Enable/Fault functions Output clamp voltage (typ): 15 V Undervoltage lockout Short-circuit limit Overload current limit Controlled output voltage ramp Thermal latch (typ): 165 °C Operating junction temp. - 40 °C to 125 °C Available in DFN10 (3x3 mm) package UL2367 Recognized - File N. E468771 Applications • • • • • Hard disk drives Solid state drives (SSD) Hard disk and SSD arrays Set-top boxes DVD and Blu-ray disc drivers Description The STEF12 is an integrated electronic fuse optimized for monitoring output current and input voltage. Connected in series to a 12 V rail, it is capable of protecting the electronic circuitry on its output from overcurrent and overvoltage. The device has a controlled delay and turn-on time. When an overload condition occurs, the STEF12 limits the output current to a predefined safe value. If the anomalous overload condition persists it goes into an open state, disconnecting the load from the power supply. If a continuous short-circuit is present on the board, when power is re-applied the E-fuse initially limits the output current to a safe value and then again goes into an open state. The device is equipped with a thermal protection circuit. The intervention of the thermal protection is signal led to the board monitoring circuits through a signal on the Fault pin. Unlike the mechanical fuses, which must be physically replaced after a single event, the Efuse does not degrade in its performance after short-circuit/thermal protection interventions and it is reset either by recycling the supply voltage or using the Enable pin. The companion chip for the 5 V power rails is also available with part number STEF05. DS7315 - Rev 8 - June 2022 For further information contact your local STMicroelectronics sales office. www.st.com STEF12 Device block diagram 1 Device block diagram Figure 1. Block diagram DS7315 - Rev 8 page 2/21 STEF12 Pin configuration 2 Pin configuration Figure 2. Pin connection (top view) GND Source dv /dt Source VCC En/fault Source I-Limit Source N/C Source Table 1. Pin description Pin n° Symbol 1 GND Ground pin dv/dt The internal dv/dt circuit controls the slew rate of the output voltage at turn-on. The internal capacitor allows a ramp-up time of around 1 ms. An external capacitor can be added to this pin to increase the ramp time. If an additional capacitor is not required, this pin should be left open. 2 Note The Enable/Fault pin is a tri-state, bi-directional interface. During normal operation the pin must be left floating, or it can be used to disable the output of the device by pulling it to ground using an open drain or open collector device. DS7315 - Rev 8 3 En/Fault 4 I-Limit 5 NC 6 to 10 VOUT/Source 11 VCC If a thermal fault occurs, the voltage on this pin goes into an intermediate state to signal a monitor circuit that the device is in thermal shutdown. It can be connected to another device of this family to cause a simultaneous shutdown during thermal events. A resistor between this pin and the Source pin sets the overload and short-circuit current limit levels. Don't leave this pin unconnected. Not connected Connected to the source of the internal power MOSFET and to the output terminal of the fuse Exposed pad. Positive input voltage must be connected to VCC. page 3/21 STEF12 Maximum ratings 3 Maximum ratings Table 2. Absolute maximum ratings Symbol VCC Parameter Value Positive power supply voltage (steady state) -0.3 to 18 Positive power supply voltage (max 100 ms) -0.3 to 25 Unit V VOUT/source (max 100 ms) -0.3 to VCC+0.3 V I-Limit (max 100 ms) -0.3 to 25 V En/Fault -0.3 to 7 V dv/dt -0.3 to 7 V Operating junction temperature range -40 to 125 °C TSTG Storage temperature range -65 to 150 °C TLEAD Lead temperature (soldering) 10 sec 260 °C Top 1. The thermal limit is set above the maximum thermal rating. It is not recommended to operate the device at temperatures greater than the maximum ratings for extended periods of time. Note: Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Table 3. Thermal data Symbol Parameter Value Unit RthJA Thermal resistance junction-ambient 52.7 °C/W RthJC Thermal resistance junction-case 17.4 °C/W Table 4. ESD performance Symbol ESD DS7315 - Rev 8 Parameter ESD protection Test conditions Value Unit HBM 2 kV MM 200 V CDM 500 V page 4/21 STEF12 Electrical characteristics 4 Electrical characteristics Table 5. Electrical characteristics VCC = 12 V, VEN = 3.3 V, CI = 10 µF, CO = 47 µF, TJ = 25 °C (unless otherwise specified). Symbol Parameter Test conditions Min. Typ. Max. Unit Under/Overvoltage protection VClamp Output clamping voltage VCC = 18 V 13.8 15 16.2 V VUVLO Undervoltage lockout Turn-on, voltage rising 7.7 8.5 9.3 V VHyst UVLO hysteresis 0.80 V 350 µs Power MOSFET tdly Delay time Enabling of chip to ID = 100 mA with a 1 A resistive load (1) RDSon On-resistance VOFF Off state output voltage ID Continuous current -40 °C < TJ < 125 °C 35 53 (2) 70 82 VCC = 18 V, VGS = 0, RL= infinite 40 0.5in2 pad, TA = 25 °C (1) 3.6 Minimum copper, TA = 80 °C 1.7 100 mΩ mV A Current limit IShort ILim Short-circuit current limit RLimit = 22 Ω Overload current limit RLimit = 22 Ω Output voltage ramp time Enable to VOUT = 11.7 V, No Cdv/dt 0.5 0.9 2.6 ms Low level input voltage Output disabled 0.35 0.58 0.81 V Intermediate level input voltage Thermal fault, output disabled 0.82 1.4 1.95 V High level input voltage Output enabled 1.96 2.64 3.3 V 3.4 4.3 5.4 V -10 -30 µA 3.3 4.4 5.5 4.4 A A dv/dt circuit dv/dt Enable/Fault VIL VI(INT) VIH VI(MAX) High state maximum voltage IIL Low level input current (sink) VEnable = 0 V II High level leakage current for external switch VEnable = 3.3 V 1 µA Maximum fan-out for fault signal Total numbers of chips that can be connected to this pin for simultaneous shutdown 3 Units Total device IBias Bias current Vmin Minimum operating voltage Device operational 1.5 Thermal shutdown 1 2 7.6 mA V Thermal latch TSD Shutdown temperature (1) 165 °C 1. Pulse test: Pulse width = 300 µs, Duty cycle = 2%. 2. Guaranteed by design, but not tested in production. DS7315 - Rev 8 page 5/21 STEF12 Typical application 5 Typical application Figure 3. Application circuit Figure 4. Typical HDD application circuit 5.1 Operating modes 5.1.1 Turn-on When the input voltage is applied, the Enable/Fault pin goes up to the high state, enabling the internal control circuitry. After an initial delay time of typically 350 µs, the output voltage is supplied with a slope defined by the internal dv/dt circuitry. If no additional capacitor is connected to dv/dt pin, the total time from the Enable signal going high and the output voltage reaching the nominal value is around 1 ms (refer to Figure 5, Figure 15). 5.1.2 Normal operating condition The STEF12 E-fuse behaves like a mechanical fuse, buffering the circuitry on its output with the same voltage shown at its input, with a small voltage fall due to the N-channel MOSFET RDSOn. 5.1.3 Output voltage clamp This internal protection circuit clamps the output voltage to a maximum safe value, typically 15 V, if the input voltage exceeds this threshold. DS7315 - Rev 8 page 6/21 STEF12 R limit calculation 5.1.4 Current limiting When an overload event occurs, the current limiting circuit reduces the conductivity of the power MOSFET, in order to clamp the output current at the value selected externally by means of the limiting resistor RLimit (Figure 3). 5.1.5 Thermal shutdown If the device temperature exceeds the thermal latch threshold, typically 165 °C, the thermal shutdown circuitry turns the power MOSFET off, thus disconnecting the load. The EN/Fault pin of the device is automatically set at an intermediate voltage, in order to signal the overtemperature event. In this condition the E-fuse can be reset either by cycling the supply voltage or by pulling down the EN pin below the Vil threshold and then releasing it. 5.2 R limit calculation As shown in Figure 3, the device uses an internal N-channel sense FET with a fixed ratio, to monitor the output current and limit it at the level set by the user. The RLimit value for achieving the requested current limitation can be estimated by using the following theoretical formula, together with the graph in Figure 13. 5.3 RLimit = I 95 Sℎort Cdv/dt calculation (1) Connecting a capacitor between the Cdv/dt pin and GND allows the modification of the output voltage ramp-up time. Given the desired time interval Δt during which the output voltage goes from zero to its maximum value, the capacitance to be added on the Cdv/dt pin can be calculated using the following theoretical formula: Cdv/dt = 3.92 × 10−8Δt − 35.3 × 10−12 (2) Where Cdv/dt is expressed in Farads and the time in seconds. The addition of an external Cdv/dt influences also the initial delay time, defined as the time between the Enable signal going high and the start of the VOUT slope (figure below). The contribution of the external capacitor to this time interval can be estimated by using the following theoretical formula: delay time s = 35 × 10−5 + 71 × 105 × Cdv/dt F (3) Figure 5. Delay time and VOUT ramp-up time 12 10 delay time ramp -up time En/Fault VOUT V 8 6 4 2 0 Time DS7315 - Rev 8 page 7/21 STEF12 Enable/Fault pin 5.4 Enable/Fault pin The Enable/Fault pin has the dual function of controlling the output of the device and, at the same time, of providing information about the device status to the application. When it is used as a standard Enable pin, it should be connected to an external open-drain or open-collector device. In this case, when it is pulled at low logic level, it turns the output of the E-Fuse off. If this pin is left floating, since it has internal pull-up circuitry, the output of the E-Fuse is kept ON, in normal operating conditions. In case of thermal fault, the pin is pulled to an intermediate state (figure below). This signal can be provided to a monitor circuit, informing it that a thermal shutdown has occurred, or it can be directly connected to the Enable/ Fault pins of other STEFxx devices on the same application in order to achieve a simultaneous enable/disable feature. When a thermal fault occurs, the device can be reset either by cycling the supply voltage or by pulling down the Enable pin below the Vil threshold and then releasing it. Figure 6. Enable/Fault pin status 5 Normal operating condition EN/Fault voltage [V] 4 3 2 Thermal fault condition 1 Off/Reset 0 DS7315 - Rev 8 time page 8/21 STEF12 Typical characteristics 6 Typical characteristics The following plots are referred to the typical application circuit and, unless otherwise noted, at TA = 25 °C. Figure 8. UVLO voltage vs. temperature Figure 7. Clamping voltage vs. temperature 9.5 16.5 VCC = 18 V VCC = from 0 to 12 V, RLIMIT = 15 Ω 9.3 16 9.1 UVLO Voltage (V) Output Voltage (V) 8.9 15.5 15 8.7 8.5 8.3 8.1 14.5 7.9 14 7.7 7.5 13.5 -40 -25 0 25 55 85 125 -40 150 -25 0 25 55 85 125 150 Temperature °C Temperature °C Figure 9. UVLO hysteresis vs. temperature Figure 10. Off-state voltage vs. temperature 1.4 250 VCC from 12 to 0 V, RLIMIT = 15 Ω VCC = 18 V, VGS = 0, RL = infinite 1.2 1 Output Voltage (mV) UVLO Hysteresys (V) 200 0.8 0.6 150 100 50 0.4 0 0.2 -40 -25 0 25 55 Temperature °C DS7315 - Rev 8 85 125 150 -40 -25 0 25 55 85 125 150 Temperature °C page 9/21 STEF12 Typical characteristics Figure 11. Bias current (device operational) Figure 12. ON resistance vs. temperature 90 3 VCC = 12 V, RLIMIT = 15 Ω, ILOAD = 1 A VCC = 12 V, RLIMIT = 15 Ω 80 2.5 70 RDSON (mΩ) Current (mA) 2 1.5 1 60 50 40 0.5 30 20 0 -40 -25 0 25 55 85 125 -40 150 -25 0 25 55 125 Temperature °C Temperature °C Figure 13. Current limit vs. RLimit Figure 14. Thermal latch delay vs. power 800 9.00 VCC = 12 V, T = 25 °C 8.00 Thermal Action Time (ms) 7.00 Limit & Short Current (A) 85 ILIM 6.00 ISHORT 5.00 4.00 3.00 2.00 T=25 °C 80 T=55 °C T=85 °C 8 1.00 0.00 0 10 20 30 40 50 External Sensing Resistor (Ω) DS7315 - Rev 8 60 70 80 0.8 0 10 20 30 40 50 60 Power (W) page 10/21 STEF12 Typical characteristics Figure 15. VOUT ramp-up vs. enable Figure 17. Line transient DS7315 - Rev 8 Figure 16. VOUT clamping Figure 18. Startup into output short-circuit page 11/21 STEF12 Typical characteristics Figure 19. Thermal latch from 2 A load to short-circuit DS7315 - Rev 8 Figure 20. Startup into output short-circuit (fast rise) page 12/21 STEF12 Package information 7 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 7.1 DFN10L (3x3 mm) package information Figure 21. DFN10L (3x3 mm) package outline DS7315 - Rev 8 page 13/21 STEF12 DFN10L (3x3 mm) package information Table 6. DFN10L (3x3 mm) mechanical data Dim. A mm Min. Typ. Max. 0.80 0.90 1.00 0.02 0.05 0.65 0.80 A1 A2 0.55 A3 0.20 b 0.18 0.25 0.30 D 2.85 3.00 3.15 D2 2.20 E 2.85 E2 1.40 E3 0.230 E4 0.365 e L 2.70 3.00 3.15 1.75 0.50 0.30 0.40 ddd 0.50 0.08 Figure 22. DFN10L (3x3 mm) recommended footprint DS7315 - Rev 8 page 14/21 STEF12 DFN10L (3x3 mm) packing information 7.2 DFN10L (3x3 mm) packing information Figure 23. DFN10L (3x3) tape and reel outline Note: Drawing not in scale Table 7. DFN10L (3x3) tape and reel mechanical data Dim. mm Min. Typ. A 330 C 12.8 D 20.2 N 60 13.2 T DS7315 - Rev 8 Max. 18.4 Ao 3.3 Bo 3.3 Ko 1.1 Po 4 P 8 page 15/21 STEF12 Ordering information 8 Ordering information Table 8. Order codes DS7315 - Rev 8 Order code Package Packaging STEF12PUR DFN10 (3x3 mm) Tape and reel page 16/21 STEF12 Revision history Table 9. Document revision history DS7315 - Rev 8 Date Revision Changes 15-Jul-2011 1 Initial release. 08-Aug-2011 2 Modified definition for Top in Table 3: Absolute maximum ratings. 14-Dec-2011 3 Removed Vdv/dt and Idv/dt rows from dv/dt circuit Table 6 on page 6. 06-Mar-2012 4 Updated: package mechanical data Table 7 on page 17, Figure 21 on page 16 and Figure 24 on page 19. 14-Jan-2013 5 Updated: package mechanical data Table 7 on page 17 and Figure 21 on page 16. 03-Aug-2015 6 Updated Equation 2, Equation 3 and Section 7: Package information. Minor text changes. 07-Feb-2020 7 Updated Figure 17 and Figure 18. 27-Jun-2022 8 Added Features on the cover page. page 17/21 STEF12 Contents Contents 1 Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 4 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 Typical application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5.1 Operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5.1.1 Turn-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5.1.2 Normal operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5.1.3 Output voltage clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5.1.4 Current limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5.1.5 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5.2 R limit calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5.3 Cdv/dt calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5.4 Enable/Fault pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6 Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 8 7.1 DFN10L (3x3 mm) package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.2 DFN10L (3x3 mm) packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 DS7315 - Rev 8 page 18/21 STEF12 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ESD performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Electrical characteristics VCC = 12 V, VEN = 3.3 V, CI = 10 µF, CO = 47 µF, TJ = 25 °C (unless otherwise specified). 5 DFN10L (3x3 mm) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 DFN10L (3x3) tape and reel mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 DS7315 - Rev 8 page 19/21 STEF12 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. DS7315 - Rev 8 Block diagram . . . . . . . . . . . . . . . . . . . . Pin connection (top view) . . . . . . . . . . . . . Application circuit . . . . . . . . . . . . . . . . . . Typical HDD application circuit . . . . . . . . . Delay time and VOUT ramp-up time . . . . . . Enable/Fault pin status . . . . . . . . . . . . . . Clamping voltage vs. temperature . . . . . . . UVLO voltage vs. temperature . . . . . . . . . UVLO hysteresis vs. temperature . . . . . . . Off-state voltage vs. temperature . . . . . . . Bias current (device operational). . . . . . . . ON resistance vs. temperature . . . . . . . . . Current limit vs. RLimit . . . . . . . . . . . . . . . Thermal latch delay vs. power . . . . . . . . . VOUT ramp-up vs. enable . . . . . . . . . . . . . VOUT clamping . . . . . . . . . . . . . . . . . . . . Line transient . . . . . . . . . . . . . . . . . . . . . Startup into output short-circuit . . . . . . . . . Thermal latch from 2 A load to short-circuit. Startup into output short-circuit (fast rise) . . DFN10L (3x3 mm) package outline . . . . . . DFN10L (3x3 mm) recommended footprint . DFN10L (3x3) tape and reel outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 . 3 . 6 . 6 . 7 . 8 . 9 . 9 . 9 . 9 10 10 10 10 11 11 11 11 12 12 13 14 15 page 20/21 STEF12 IMPORTANT NOTICE – READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgment. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2022 STMicroelectronics – All rights reserved DS7315 - Rev 8 page 21/21