STEVAL-IFW002V1

STEVAL-IFW002V1 Real-time Ethernet Xilinx FPGA extension board for the STEVAL-IFW001V1 Data Brief Features ■ Xilinx Spartan-3E FPGA device for Ethernet RT IP ■ Platform Flash (XCF04S) ■ CN1, CN2 connectors for plug-in connection with STEVAL-IFW001V1 demonstration board ■ P1 programming connector for FPGA platform Flash (6-pin) ■ P6 connector for RS485 communication through the ST3485EB transceiver ■ 8 general-purpose LEDs ■ 8-bit DIP switch for general configuration (e.g. device address) Description ) s ( ct u d o r P e t e l o )- The STEVAL-IFW002V1 is an FPGA extension of the STEVAL-IFW001V1. This extension board was designed to handle a real-time (RT) Ethernet IP (e.g. RT HUB for Powerlink, IEEE1588, EtherCAT IP, etc.). It can also be used for evaluation of other IPs connected to the STR912FA microcontroller, such as timers, communication I/Fs. Communication between the STR912FA demonstration board and the extension can be achieved through a medium independent interface (MII), external memory interface (EMI), SPI™, GPIOs or by other methods. s b O STEVAL-IFW002V1 s ( t c u d o r P e t e l o s b O RT Ethernet evaluation requires both the STEVAL-IFW0001V1 demonstration board and STEVAL-IFW0002V1 extension board. Typically, the STR912FA microcontroller communicates with the on-extension real-time Ethernet logic which, in turn, communicates with the two on-board Ethernet transceivers and the microcontroller. September 2008 Rev 1 For further information contact your local STMicroelectronics sales office. 1/7 www.st.com 7 2/7 4.7 kΩ 4.7 kΩ 4.7 kΩ 4.7 kΩ 4.7 kΩ 4.7 kΩ 4.7 kΩ 4.7 kΩ R9 R10 R11 R12 R13 R14 R15 R16 ADD0 ADD1 ADD2 ADD3 ADD4 ADD5 ADD6 ADD7 1 2 3 4 5 6 7 8 SW DIP-8 S1 MII_TX_ER_1 MII_TX_EN_1 MII_TXD1_1 MII_TXD3_1 MII_CRS_1 MII_RX_DV_1 MII_RXD1_1 MII_RXD3_1 RESET_OUT 16 15 14 13 12 11 10 9 EMI_P84 EMI_P85 EMI_P86 SPI_P25_MOSI EMI_P91 EMI_P93 SPI_P26_MISO EMI_P95 EMI_P97 EMI_P54 EMI_ALE MII_RXD1 MII_RXD3 MII_RX_DV 3.3 V 1 3 5 7 9 11 13 15 17 19 21 MII_COL 23 MII_TXD2 25 MII_TXD0 27 MII_RX_ER 29 MII_CRS_2 31 MII_TXD3_2 33 MII_TXD1_2 35 MII_TX_EN_2 37 MII_TX_ER_2 39 MII_RX_CLK_ 2 41 MII_RXD0_2 43 MII_RXD2_2 45 1.8 V MII_MDC 47 49 EMI_P82 MII_TX_EN PHY_CLK EMI_WR/WRL EMI_P7 5 EMI_P7 3 EMI_P7 2 EMI_P7 0 1.8 V EMI_P7 6 CN2 d o r 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 EMI _P74 EMI _P83 EMI _P81 EMI _P80 EMI_WRH MII _CRS MII _TXD3 MII _TXD1 MII_MDINT_2 MII_COL_2 MII _TXD2_2 MII _TXD0_2 MII_TX_CLK_ 2 MII _RX_ER_2 MII _RX_DV_2 MII _RXD1_2 MII _RXD3_2 MII_MDIO EMI _P71 EMI _P77 t c u C2 100 nF 3.3 V ST3485EB 3.3 V 3.3 V RS485 C6 100 nF 1.8 V 3.3 V P6 C3 100 nF 1.8 V R28 FPGA_Interrupt1 R27 RS485_P50_Tx C4 100 nF 1 2 3 4 Header 4 C5 100 nF 3.3 V R30 120 NA u d o C1 100 nF 3.3 V 0Ω 0Ω 0Ω 0Ω R26 RS485_P51_Rx R25 FPGA_Interrupt0 r P e R29 390 Ω RO VCC RE B RS485_P22_nDE DE A RS485_P50_Tx DI GND RS485_P51_Rx U6 Header 25 x 2 module connector ) (s s b O t e l o 3.3 V 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 3.3 V GP_LED8 GP_LED7 GP_LED6 GP_LED5 GP_LED4 GP_LED3 GP_LED2 GP_LED1 330 Ω R8 330 Ω R7 330 Ω R6 330 Ω R5 330 Ω R4 330 Ω R3 330 Ω R2 330 Ω R1 1 1 1 1 1 1 1 1 AI14571 green 2 LD8 green 2 LD7 green 2 LD6 green 2 LD5 green 2 LD4 green 2 LD3 green 2 LD2 green 2 LD1 Figure 1. Header 25 x 2 module connector 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 P e t e l o RS485_P22_nDE FPGA_Done SPI_P24_SCL K EMI _P87 EMI _P90 EMI _P92 EMI _P94 SPI_P27_NSS EMI _P96 MII_TX_CLK MII _RXD0 EMI_RD MII _RXD2 MII_RX_CLK MII_MDINT_1 MII _RX_ER_1 MII_TX_CLK_1 MII _TXD0_1 MII _TXD2_1 MII_COL_1 MII_RX_CLK_1 MII _RXD0_1 MII _RXD2_1 s b O 3.3 V 1 CN1 Module connectors Extension board schematic STEVAL-IFW002V1 Extension board schematic Mobile connectors, LEDs and device address schematic ) s ( ct 104 C10 100 nF 3.3 V 3.3 V GND VCC ST 4 3 SG-210, crystal oscillator 2 1 U5 3.3 V PHY_CLK R23 0 NA 2.5 V 20 18 19 FPGA_Done 4 6 5 FLASH_CLK 3 10 FLASH_OE/RESET 8 6 5 4 3 2 1 P1 JTAG 3.3 V R18 R19 330 Ω 4.7 kΩ 3.3 V d o r t c u 11 ) (s 3 3.3 V 2.5 V FGPA_CLK 25 MHz 0Ω DEF = 1 0Ω DEF = 3 R22 3 2 1 2 R21 1 DNC DNC DNC TDO CF CEO D0 DNC DNC DNC C7 100 nF 2.5 V XCF04SVO20C GND TDI TCK TMS CLK CE OE/RESET VCCJ VCCINT VCCO U2 s b O t e l o 14 15 16 17 7 13 1 2 9 12 C8 100 nF u d o 142 154 148 136 130 124 118 110 194 184 183 175 174 169 159 204 51 43 32 26 20 14 6 101 91 81 FGPA_CLK 25 MHz 80 72 Platform Flash 71 58 57 54 C9 100 nF 3.3 V FPGA_Reload R20 4.7 kΩ 2.5 V R24 0Ω FPGA reload B1 XC3S500E-4PQ208C IP IP IP IP IP/VREF_3 IP IP IP IP IP_L10N_2/M2/GCLK1 IP_L10P_2/RDWR_B/GCLK0 IP_L07N_2/VREF_2 IP_L07P_2 IP_L02N_2 IP_L02P_2 IP IP IP IP IP/VREF_1 IP IP IP IP IP IP_L09N_0/GCLK9 IP_L09P_0/GCLK8 IP_L06N_0 IP_L06P_0 IP IP IP U1E 1 RESET_OUT TO MCU OUTPUT RESET FLASH_D0 r P e FPGA CLOCK OUT FPGA_Reload XC3S500E-4PQ208C DONE 1 155 158 157 207 2.5 V P e t e l o JTAG, Flash AI14572 2 Figure 2. PROG_B TMS TCK TDO TDI s b O U1F STEVAL-IFW002V1 Extension board schematic JTAG, Flash schematic ) s ( ct 3/7 4/7 C25 100 nF IN U4 1 C27 100 nF GND OUT LD1117AS12TR C28 100 nF 2 C29 100 nF C38 2.2 µF C37 2.2 µF 1 2.5 V 2 C19 100 nF C11 100 nF C12 100 nF ) s ( ct C33 100 nF C34 100 nF 170 117 13 67 7 149 111 92 195 66 166 44 C35 100 nF 3.3 V C36 100 nF 2.5 V C14 100 nF C22 100 nF 1.2 V 1.2 V 2.5 V C13 100 nF C21 100 nF VCCINT VCCINT VCCINT VCCINT VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX C20 100 nF XC3S500E-4PQ208C VCCO_2 VCCO_2 VCCO_2 C32 100 nF C18 100 nF C31 100 nF C17 100 nF 1.2 V C30 100 nF C16 100 nF P4 P3 59 73 88 VCCO_3 VCCO_3 VCCO_3 VCCO_1 VCCO_1 VCCO_1 VCCO_0 VCCO_0 VCCO_0 U1G r P e u d o C26 100 nF C24 100 nF 3 3 2 38 46 21 114 125 143 201 176 191 t e l o P5 2 4 GND OUT LF 25ABDT 1 s b O 1 IN U3 t c u C15 100 nF 1 121 37 95 27 182 17 131 10 198 156 ) (s P2 2 GND GND GND GND GND GND GND GND GND GND d o r XC3S500E-4PQ208C GND GND GND GND GND GND GND GND GND GND 3.3 V AI14573 C23 100 nF Figure 3. 3.3 V 3.3 V 1 s b O 105 85 208 79 188 70 173 53 141 52 P e t e l o U1H Extension board schematic STEVAL-IFW002V1 Power supply schematic STEVAL-IFW002V1 Extension board schematic Figure 4. FPGA schematic U1B U1A BANK 0 IO_L01P_0 IO_L01N_0 IO_L02P_0 O_L02N_0/VREF_0 I IO_L03P_0 IO_L03N_0 IO_L04P_0 O_L04N_0/VREF_0 I IO_L05P_0 IO_L05N_0 IO_L07P_0/GCLK4 O_L07N_0/GCL I K5 IO/VREF_0 IO_L08P_0/GCLK6 O_L08N_0/GCL I K7 O_L10P_0/GCLK10 I O_L10N_0/GCL I K11 IO IO_L11P_0 IO_L11N_0 IO_L12P_0 O_L12N_0/VREF_0 I IO_L13P_0 IO_L13N_0 IO_L14P_0 O_L14N_0/VREF_0 I IO_L15P_0 IO_L15N_0 IO_L16P_0 IO_L16N_0/HSWAP 160 161 162 163 164 165 167 168 171 172 177 178 179 180 181 185 186 187 189 190 192 193 196 197 199 200 202 203 205 206 BANK 1 IO_L01P_1/A16 IO_L01N_1/A15 IO_L02P_1/A14 IO_L02N_1/A13 IO_L03P_1 IO_L03N_1/VREF_1 IO_L04P_1 IO_L04N_1 IO_L05P_1/A12 IO_L05N_1/A11 IO_L06P_1 IO_L06N_1/VREF_1 IO_L07P_1/A10/RHCLK0 IO_L07N_1/A9/RHCL K1 IO_L08P_1/A8/RHCLK2 IO_L08N_1/A7/RHCL K3 IO_L09P_1/A6/RHCLK4 IO_L09N_1/A5/RHCL K5 IO_L10P_1/A4/RHCLK6 IO_L10N_1/A3/RHCL K7 IO_L11P_1/A2 IO_L11N_1/A1 IO_L12P_1 IO_L12N_1/A0 IO_L13P_1 IO_L13N_1 IO_L14P_1 IO_L14N_1 IO_L15P_1/HDC IO_L15N_1/LDC0 IO_L16P_1/LDC1 IO_L16N_1/LDC2 MII_MDI O MII _MDC MII _RXD3_2 MII _RXD2_2 MII _RXD1_2 MII _RXD0_2 MII _RX_DV_2 MII_RX_CLK_2 MII _RX_ER_2 MII _TX_ER_2 MII_TX_CLK_2 MII _TX_EN_2 MII _TXD0_2 MII _TXD1_2 MII _TXD2_2 MII _TXD3_2 MII_COL_2 MII_CRS_2 R17 t e l o 0 XC3S500E-4PQ208C bs MII _RXD1 MII _RXD2 MII _RXD3 MII_RX_CLK MII _RX_DV MII_MDI NT_1 MII _RX_ER_1 MII _TX_ER_1 MII_TX_CLK_1 MII _TX_EN_1 MII _TXD0_1 MII _TXD1_1 MII _TXD2_1 MII _TXD3_1 MII_COL_1 MII_CRS_1 MII_RX_CLK_1 MII _RX_DV_1 MII _RXD0_1 MII _RXD1_1 MII _RXD2_1 MII _RXD3_1 MII1 ) s ( ct u d o r P e HSWAP - use pull-ups 106 107 108 109 112 113 115 116 119 120 122 123 126 127 128 129 132 133 134 135 137 138 139 140 144 145 146 147 150 151 152 153 ADD7 ADD6 ADD5 ADD4 Device ADD3 address ADD2 ADD1 ADD0 XC3S500E-4PQ208C U1C ) s ( ct BANK 2 IO_L01P_2/CSO_B IO_L01N_2/INIT_B IO_L03P_2/DOUT/BUSY IO_L03N_2/MOSI/CSI_B IO_L04P_2 IO_L04N_2 IO_L05P_2 IO_L05N_2 IO_L06P_2 IO_L06N_2 IO_L08P_2/D7/GCLK12 I O_L08N_2/D6/GCLK13 IO/D5 IO_L09P_2/D4/GCLK14 IO_L09N_2/D3/GCLK15 IO_L11P_2/D2/GCLK2 IO_L11N_2/D1/GCLK3 IO/M1 IO_L12P_2/M0 IO_L12N_2/DIN/D0 IO_L13P_2 IO_L13N_2 IO_L14P_2/A23 IO_L14N_2/A22 IO_L15P_2/A21 IO_L15N_2/A20 IO/VREF_2 IO_L16P_2/VS2/A19 IO_L16N_2/VS1/A18 IO_L17P_2/VS0/A17 IO_L17N_2/CCLK u d o r P e s b O t e l o XC3S500E-4PQ208C 55 56 60 61 62 63 64 65 68 69 74 75 76 77 78 82 83 84 86 87 89 90 93 94 96 97 98 99 100 102 103 -O FLASH_OE/RESET GP_LED8 EMI_P84 EMI_P85 SPI_P24_SCLK EMI_P86 EMI_P87 SPI_P25_MOSI EMI_P90 EMI_P91 EMI_P92 EMI_P93 EMI_P94 SPI_P26_MISO SPI_P27_NSS EMI_P95 FLASH_D0 Platform Flash EMI_P96 EMI_P97 MII_TX_CLK EMI_P54 MII _RXD0 EMI_ALE EMI_RD FLASH_CLK U1D BANK 3 IO_L01P_3 IO_L01N_3 IO_L02P_3 IO_L02N_3/VREF_3 IO_L03P_3 IO_L03N_3 IO_L04P_3 IO_L04N_3 IO_L05P_3 IO_L05N_3 IO_L06P_3 IO_L06N_3 IO_L07P_3/LHCLK0 IO_L07N_3/LHCLK1 IO_L08P_3/LHCLK2 IO_L08N_3/LHCLK3 IO_L09P_3/LHCLK4 IO_L09N_3/LHCLK5 IO_L10P_3/LHCLK6 IO_L10N_3/LHCLK7 IO_L11P_3 IO_L11N_3 IO_L12P_3 IO_L12N_3 IO_L13P_3 IO_L13N_3 IO_L14P_3 IO_L14N_3 IO/VREF_3 IO_L15P_3 IO_L15N_3 IO_L16P_3 IO_L16N_3 XC3S500E-4PQ208C 2 3 4 5 8 9 11 12 15 16 18 19 22 23 24 25 28 29 30 31 33 34 35 36 39 40 41 42 45 47 48 49 50 MII _RX_ER MII_MDI NT_2 MII _TXD0 MII _TXD1 MII _TXD2 MII _TXD3 MII_COL MII _CRS EMI_P77 EMI_P76 EMI_P71 EMI_P70 FPGA_Interrupt1 EMI_P72 EMI_P74 EMI_P73 FPGA_Interrupt0 EMI_P75 EMI_WRH EMI_WR/WRL EMI_P80 EMI_P81 MII _TX_EN EMI_P83 EMI_P82 GP_LED1 GP LEDS GP_LED2 GP_LED3 GP_LED4 GP_LED5 GP_LED6 GP_LED7 AI14574 5/7 Revision history 2 STEVAL-IFW002V1 Revision history Table 1. Document revision history Date Revision 15-Sep-2008 1 Changes Initial release ) s ( ct u d o r P e t e l o ) (s t c u d o r P e t e l o s b O 6/7 s b O STEVAL-IFW002V1 ) s ( ct Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. u d o r P e All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. t e l o No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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