STEVAL-IME008V1

STEVAL-IME008V1 STHV749 Ultrasound Pulser IC evaluation board Data brief Description The STEVAL-IME008V1 is a product evaluation board designed around the STHV749 4-channel 7-level high voltage pulser, a state-of-the-art device designed for ultrasound imaging applications. The output waveforms can be displayed directly on an oscilloscope by connecting the scope probe to the relative BNCs. 16 preset waveforms are available to test the HV pulser under varying conditions. Features • 4-channel outputs: high voltage and low voltage BNC connectors • Load simulator using signal equivalent circuits • Possibility to set up own load simulator • 16 preset waveforms • USB connector to connect STM32 with PC and supply power to it • 4 MB serial Flash memory to host FPGA code and waveforms • Memory expansion connector to add external serial Flash • Connectors to supply high voltage and low voltage to the STHV749 output stage • LEDs to monitor the power management stage • Human machine interface to select, start and stop the generation of the preset waveforms • 25 LEDs to monitor board behavior • RoHS compliant August 2015 DocID026791 Rev 2 For further information contact your local STMicroelectronics sales office. 1/19 www.st.com BOARD_POWER_BLK MCU_3V3 MCU_3V3 FLASH_3V3 FLASH_3V3 BOARD_POWER DVDD VDDP VDDM DVDD USB_DISCONNECT USB_DISCONNECT FPGA FPGA_SPI_CCLK FPGA_SPI_MOSI FPGA_SPI_MISO1 FPGA_SPI_MISO2 FPGA_SPI_MISO3 FPGA_SPI_SEL HVP0 HVP1 HVPCW HVM0 HVM1 HVMCW HVPCW HVP1 HVP0 STM32_FLASH VDDP USB_DP USB_DP USB_DM USB_DM MCU_FPGA_PROG MCU_FPGA_INIT_B MCU_FPGA_MODE1 FPGA_MCU_DONE MCU_FPGA_OSC_EN FPGA_MCU_AWAKE MCU_FPGA_SUSPEND +VFPGA_IO_3V3 +VFPGA_CORE_1V2 HVM0 FLASH_C FLASH_DQ0 FLASH_DQ1 FLASH_DQ2 FLASH_DQ3 FLASH_nS VDDM MCU_FPGA_GPIO[0:7] HVM1 MCU_FPGA_PROG MCU_FPGA_INIT_B MCU_FPGA_MODE1 FPGA_MCU_DONE MCU_FPGA_OSC_EN FPGA_MCU_AWAKE MCU_FPGA_SUSPEND MCU_FPGA_GPIO[0:7] CW CK DATAOUT13 DATAOUT12 DATAOUT10 DATAOUT11 DATAOUT8 DATAOUT9 DATAOUT6 DATAOUT7 DATAOUT2 DATAOUT3 DATAOUT0 DATAOUT1 THSD_EN DATAOUT[0:15] DVDD VDDP HVP0 HVP1 HVPCW DVDD CK THSD_EN SEL CW IN4_1 IN4_2 IN3_2 IN4_0 IN3_0 IN3_1 IN2_1 IN2_2 IN1_2 IN2_0 IN1_0 IN1_1 VDDM STHV749 STHV749_BLK DATAOUT4 DATAOUT5 DATAOUT[0:15] +VFPGA_IO_3V3 FPGA_GPIO[0:7] HVMCW DocID026791 Rev 2 VDDM FPGA_BLK VDDP HVM0 HVM1 HVP0 HVM1 HVMCW HVP_CW HVP1 2/19 HVM_CW 1 HVM0 STM32_FLASH_BLK Schematic diagrams STEVAL-IME008V1 Schematic diagrams Figure 1. STEVAL-IME008V1 circuit schematic (1 of 16) GSPG30072014DI1135 +VFPGA_CORE_1V2 C7 1uF USB_5V 1 R1 1M USB_5V C11 33nF VIN U2 DM DP USB_miniB SOT23-5L VOUT 5 USB_3V3 C8 2.2uF 6.3V LDS3985M33R RS (515-1995) Molex (54819-0572) ID nc GND SHELL SHELL SHELL SHELL VBUS DM DP CN1 C3 4.7nF 4 5 6 7 8 9 1 2 3 USB INH 3 BYPS 4 GND DocID026791 Rev 2 2 3 2 1 D3 USBUF02W6 D2 Grd 3.3V DM 4 USB_DISCONNECT USB_DM USB_DP USB_DISCONNECT 5 U1 SOTT323-6L 6 DP D4 D1 R90 56R D26 RED USB ON Kingbright KP2012SURC RS: 466-3829 Farnell: 8529930 LED 0805 C8 Details: DigiKey (478-2552-2-ND) - AVX (TACL225M006XTA) Package 0603 C7 Details: Digikey (445-4998-2-ND) - TDK (C1005X5R0J105K) Package 0402 USB_DISCONNECT USBDM USBDP USBDM USBDP STEVAL-IME008V1 Schematic diagrams Figure 2. STEVAL-IME008V1 circuit schematic (2 of 16) GSPG30072014DI1140 3/19 19 4 3 DocID026791 Rev 2 1 2 D1 SM2T3V3A J41 1 2 NOT ASSEMBLY C12 4u7 6.3V EXT_3V3 MMS228T nc ON_2a COM_1a ON_1a DVDD nc ON_2b COM_1b ON_1b J4 Details Phoenix Contact (Mfg Code MPT 0.5/2-2.54) RS (220-4260) C12 and C13 Detail TDK (C1608X5R0J475K) - Digikey (445-5178-2-ND) Dimension 0603 - EIA 1608 3V3 3V3 Connector J4 SW1 Details: SW1 RS 711-8329 KNITTER-SWITCH (MMS228T) EXT_3V3 FLASH_3V3 2 1 C13 4u7 6.3V 1 4 ST1S12xx EN Vin U3 SW FB/Vo +VFPGA_IO_3V3 FLASH_3V3 5 3 MCU L1 R124 56 D27 RED L1 Detail TDK (VLF4012AT-2R2M1R5) - RS (614-3147) C14 Detail TDK (C2012X7R1A106K) - DIGIKEY (445-6857-2-ND) Dimension 0805 - EIA 2012 RED D28 FPGA R125 56 5 6 7 8 GND 4/19 2 USB_3V3 3.3V Power Management 2.2uH C14 10u 10V MCU_3V3 +VFPGA_CORE_1V2 Schematic diagrams STEVAL-IME008V1 Figure 3. STEVAL-IME008V1 circuit schematic (3 of 16) GSPG30072014DI1150 STEVAL-IME008V1 Schematic diagrams Figure 4. STEVAL-IME008V1 circuit schematic (4 of 16) HVPCW HVP1 HVP0 22000n 100V 22000n 100V C1 C78 100V 100V J1 Details RS 2X(193-0564) Phoenix Contact (Mfg Code MKDS 1.5/2-5.08) GND_POWER J2 LV 100V DVDD VDDP VDDM VDDM C6 DVDD VDDP GND VDDM 1 2 3 4 C4 J2 Details RS 2X(193-0564) 22000n 16V Phoenix Contact (Mfg Code 16V MKDS 1.5/2-5.08) 22000n 16V 22000n 16V 16V HVPCW HVP1 HVP0 GND C2 22000n 100V DVDD VDDP C5 HVP LOW POWER J1 1 2 3 4 HVPCW HVP1 HVP0 + HIGH VOLTAGE STHV800 Power Management 16V J3 HVMCW HVM1 HVM0 HVMCW HVM1 HVM0 22000n 100V 22000n 100V C79 C9 100V 100V C10 22000n 100V 100V HVM HVMCW HVM1 HVM0 GND 1 2 3 4 J3 Details RS 2X(193-0564) Phoenix Contact (Mfg Code MKDS 1.5/2-5.08) - HIGH VOLTAGE GND_POWER C1, C2, C9, C10, C15, C16 Details:GND_POWER Digikey (445-5217-2-ND) - TDK (CKG57NX7S2A226M) Package 6.5mm x 5.5 mm C4, C5, C6 Details: Digikey (445-1436-2-ND) - TDK (C3225X5R1C226M) Package 1210 - EIA 3225 R2 R123 0 0 GND_POWER GSPG30072014DI1155 DocID026791 Rev 2 GND_SHIELD 5/19 19 6/19 DocID026791 Rev 2 IO_0_L01N_VREF IO_0_L01P_HSWAPEN IO_0_L02N IO_0_L02P IO_0_L03N IO_0_L03P IO_0_L04N IO_0_L04P IO_0_L05N IO_0_L05P IO_0_L06N IO_0_L06P IO_0_L07N IO_0_L07P IO_0_L08N_VREF IO_0_L08P IO_0_L09N IO_0_L09P IO_0_L10N IO_0_L10P IO_0_L11N IO_0_L11P IO_0_L32N IO_0_L32P IO_0_L33N IO_0_L33P IO_0_L34N_GCLK18 IO_0_L34P_GCLK19 IO_0_L35N_GCLK16 IO_0_L35P_GCLK17 IO_0_L36N_GCLK14 IO_0_L36P_GCLK15 IO_0_L37N_GCLK12 IO_0_L37P_GCLK13 IO_0_L38N_VREF IO_0_L38P IO_0_L39N IO_0_L39P IO_0_L40N IO_0_L40P IO_0_L41N IO_0_L41P IO_0_L42N IO_0_L42P IO_0_L47N IO_0_L47P IO_0_L50N IO_0_L50P IO_0_L51N IO_0_L51P IO_0_L62N_VREF IO_0_L62P IO_0_L63N_SCP6 IO_0_L63P_SCP7 IO_0_L64N_SCP4 IO_0_L64P_SCP5 IO_0_L65N_SCP2 IO_0_L65P_SCP3 IO_0_L66N_SCP0 IO_0_L66P_SCP1 FPGA - Bank 0 XC6SLX16-2CSG324C U4A C4 D4 A2 B2 C6 D6 A3 B3 A4 B4 A5 C5 E6 F7 A6 B6 E8 E7 A7 C7 C8 D8 F8 G8 A8 B8 C9 D9 A9 B9 C11 D11 A10 C10 F9 G9 A11 B11 F10 G11 A12 B12 E11 F11 C12 D12 A13 C13 E12 F12 A14 B14 E13 F13 A15 C15 C14 D14 A16 B16 Diff. pair DATAOUT8 Diff. pair DATAOUT9 Diff. pair DATAOUT10 Diff. pair DATAOUT11 Diff. pair DATAOUT12 Diff. pair DATAOUT13 Diff. pair DATAOUT14 Diff. pair DATAOUT15 Diff. pair CW IDLE_STATE0 IDLE_STATE1 HI_Z THSD_EN HSWAPEN Diff. pair DATAOUT3 Diff. pair DATAOUT4 Diff. pair DATAOUT2 Diff. pair DATAOUT1 Diff. pair DATAOUT0 Diff. pair DATAOUT5 Diff. pair DATAOUT6 Diff. pair DATAOUT7 Diff. pair CK R120 10K 0402 DATAOUT[0:15] THSD_EN R121 10K 0402 CW DATAOUT[0:15] CK R122 10K 0402 NOT ASSEMBLY JUMPER J5 HSWAPEN 1 2 R3 10K 0402 +VFPGA_IO_3V3 Jumper J5 is used to control I/O pullups during FPGA configuration. +VFPGA_IO_3V3 C16 10uF 10V 0805 2 2 2 FPGA DISCONNECT NOT ASSEMBLY THESE JUMPERS J35 1 J36 1 J37 1 IDLE STATE C15 100n 0402 CK CW DATAOUT0 DATAOUT1 DATAOUT9 DATAOUT13 DATAOUT10 DATAOUT14 DATAOUT6 DATAOUT15 DATAOUT7 DATAOUT8 DATAOUT5 DATAOUT11 THSD_EN DATAOUT4 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 STHV748 I/O CONNECTOR HEADER 17X2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 NOT ASSEMBLY DATAOUT3 DATAOUT12 DATAOUT2 +VFPGA_IO_3V3 C17 10uF 10V 0805 Open J37 (default) to connect FPGA outputs Close J37 to disconnect outputs (High-Z) Configure J35 and J36 to setup outputs idle state as follows: 00 - (J35 and J36 open) --> High-Z (default) 01 - (J35 closed and J36 open) --> Clamp/HVR_SW 11 - (J35 and J36 closed) --> High-Z 10 - (J35 open and J36 closed) --> Clamp C18 100n 0402 C16 and C17 Details: TDK (C2012X7R1A106K) - DIGIKEY (445-6857-2-ND) Dimension 0805 - EIA 2012 Jumpers J35, J36 and J37 are used to set dataout output state. +VFPGA_IO_3V3 J6 Open (default) to float I/O output during FPGA configuration. Set jumper 1:2 to enable I/O pullups during FPGA configuration. Schematic diagrams STEVAL-IME008V1 Figure 5. STEVAL-IME008V1 circuit schematic (5 of 16) GSPG30072014DI1200 STEVAL-IME008V1 Schematic diagrams Figure 6. STEVAL-IME008V1 circuit schematic (6 of 16) U4B FPGA - Bank 1 F16 F15 C18 C17 G14 F14 D18 D17 G13 H12 E18 E16 K13 K12 F18 F17 H14 H13 H16 H15 G18 G16 K14 J13 L13 L12 K16 K15 L16 L15 H18 H17 J18 J16 K18 K17 L18 L17 M18 M16 N18 N17 P18 P17 N16 N15 T18 T17 U18 U17 N14 M14 M13 L14 P16 P15 FPGA_PMOD1_P2 FPGA_PMOD1_P1 FPGA_PMOD1_P4 FPGA_PMOD1_P3 FPGA_PMOD1_P8 FPGA_PMOD1_P7 FPGA_PMOD1_P10 FPGA_PMOD1_P9 FPGA_PMOD2_P2 FPGA_PMOD2_P1 FPGA_PMOD2_P4 FPGA_PMOD2_P3 FPGA_PMOD2_P8 FPGA_PMOD2_P7 FPGA_PMOD2_P10 FPGA_PMOD2_P9 CTRL_LED1 CTRL_LED0 SEL_PROG_PB FPGA_CLK_66MHZ START_PB STOP_PB FPGA USER I/O FPGA_RESET J7 FPGA_USER_IO_0 FPGA_USER_IO_1 FPGA_USER_IO_2 FPGA_USER_IO_3 FPGA_USER_IO_4 FPGA_USER_IO_5 FPGA_USER_IO_6 FPGA_USER_IO_7 FPGA_USER_IO_8 FPGA_USER_IO_9 FPGA_USER_IO_10 FPGA_USER_IO_11 FPGA_USER_IO_12 FPGA_USER_IO_13 FPGA_USER_IO_14 FPGA_USER_IO_15 CTRL_LED3 CTRL_LED2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 NOT ASSEMBLY 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 HEADER 16X2 TP1 TEST POINT FPGA_DOUT_BUSY FPGA_AWAKE XC6SLX16-2CSG324C 1 IO_1_L01N_A24_VREF IO_1_L01P_A25 IO_1_L29N_A22_M1A14 IO_1_L29P_A23_M1A13 IO_1_L30N_A20_M1A11 IO_1_L30P_A21_M1RESET IO_1_L31N_A18_M1A12 IO_1_L31P_A19_M1CKE IO_1_L32N_A16_M1A9 IO_1_L32P_A17_M1A8 IO_1_L33N_A14_M1A4 IO_1_L33P_A15_M1A10 IO_1_L34N_A12_M1BA2 IO_1_L34P_A13_M1WE IO_1_L35N_A10_M1A2 IO_1_L35P_A11_M1A7 IO_1_L36N_A8_M1BA1 IO_1_L36P_A9_M1BA0 IO_1_L37N_A6_M1A1 IO_1_L37P_A7_M1A0 IO_1_L38N_A4_M1CLKN IO_1_L38P_A5_M1CLK IO_1_L39N_M1ODT IO_1_L39P_M1A3 IO_1_L40N_GCLK10_M1A6 IO_1_L40P_GCLK11_M1A5 IO_1_L41N_GCLK8_M1CASN IO_1_L41P_GCLK9_IRDY1_M1RASN IO_1_L42N_GCLK6_TRDY1_M1LDM IO_1_L42P_GCLK7_M1UDM IO_1_L43N_GCLK4_M1DQ5 IO_1_L43P_GCLK5_M1DQ4 IO_1_L44N_A2_M1DQ7 IO_1_L44P_A3_M1DQ6 IO_1_L45N_A0_M1LDQSN IO_1_L45P_A1_M1LDQS IO_1_L46N_FOE_B_M1DQ3 IO_1_L46P_FCS_B_M1DQ2 IO_1_L47N_LDC_M1DQ1 IO_1_L47P_FWE_B_M1DQ0 IO_1_L48N_M1DQ9 IO_1_L48P_HDC_M1DQ8 IO_1_L49N_M1DQ11 IO_1_L49P_M1DQ10 IO_1_L50N_M1UDQSN IO_1_L50P_M1UDQS IO_1_L51N_M1DQ13 IO_1_L51P_M1DQ12 IO_1_L52N_M1DQ15 IO_1_L52P_M1DQ14 IO_1_L53N_VREF IO_1_L53P IO_1_L61N IO_1_L61P IO_1_L74N_DOUT_BUSY IO_1_L74P_AWAKE FPGA_MCU_AWAKE GSPG30072014DI1205 DocID026791 Rev 2 7/19 19 Schematic diagrams STEVAL-IME008V1 Figure 7. STEVAL-IME008V1 circuit schematic (7 of 16) 66MHZ EXTERNAL OSCILLATOR When using backup oscillator X1, R126 have to be mounted and R6 must be unplaced. +VFPGA_IO_3V3 C19 100nF R126 10k BACKUP OF U5 MCU_FPGA_OSC_EN C20 10nF U5 X1 1 OE ST VCC GND OUT 4 2 3 2 MCU_FPGA_OSC_EN 6 VCC 3 7 n/c 8 R7 1 FPGA_CLK_66MHZ PDN VCC n/c GND OUT GND R6 10K NM 4 5 33R2 DS1088LU-66 Place R7 (1%) close to the clock source DS1088LU-66 device 66MHZ OSC PERIPHERRAL MODULE (PMOD) +VFPGA_IO_3V3 +VFPGA_IO_3V3 C25 100nF C26 10uF 10V 0805 C28 100nF C27 10uF 10V 0805 PMOD1 NOT ASSEMBLY J8 FPGA_PMOD1_P1 FPGA_PMOD1_P3 FPGA_PMOD1_P7 FPGA_PMOD1_P9 Two right-angle, 12-pin (2 x 6 female) Peripheral Module (PMOD) headers (J8, J9) are interfaced to the FPGA, with each header providing 3.3 V power, ground, and eight I/O's. These headers may be utilized as general-purpose I/Os or may be used to interface to PMODs. J6 and J8 are placed in close proximity (0'9" -centers) on the PCB in order to support dual PMODs. 1 3 5 7 9 11 SX 2 4 6 8 10 12 FPGA_PMOD1_P2 FPGA_PMOD1_P4 FPGA_PMOD1_P8 FPGA_PMOD1_P10 C26, C27, C30 and C31 Detail HEADER 6X2 TDK (C2012X7R1A106K) - DIGIKEY (445-6857-2-ND) Dimension 0805 - EIA 2012 +VFPGA_IO_3V3 +VFPGA_IO_3V3 C29 100nF C30 10uF 10V 0805 C31 10uF 10V 0805 C32 100nF PMOD2 J9 FPGA_PMOD2_P1 FPGA_PMOD2_P3 FPGA_PMOD2_P7 FPGA_PMOD2_P9 1 3 5 7 9 11 NOT ASSEMBLY DX 2 4 6 8 10 12 FPGA_PMOD2_P2 FPGA_PMOD2_P4 FPGA_PMOD2_P8 FPGA_PMOD2_P10 HEADER 6X2 GSPG30072014DI1210 8/19 DocID026791 Rev 2 STEVAL-IME008V1 Schematic diagrams Figure 8. STEVAL-IME008V1 circuit schematic (8 of 16) PUSHBUTTONS +VFPGA_IO_3V3 +VFPGA_IO_3V3 R4 10K 0402 SEL_PROG_PB R5 10K 0402 START_PB SW PUSHBUTTON-DPST C21 100nF SW2 SW PUSHBUTTON-DPST C22 100nF SW3 PROGRAM +VFPGA_IO_3V3 START +VFPGA_IO_3V3 SW PUSHBUTTON-DPST R8 10K 0402 STOP_PB SW5 FPGA RESET FPGA_RESET SW PUSHBUTTON-DPST C23 100nF SW4 R9 10K 0402 C24 100nF STOP SW2, SW3, SW4, Details RS (378-6527) CTRL LED R10 D2 CTRL_LED0 Near START button 56R 0402 R11 GREEN D3 CTRL_LED1 56R 0402 R12 GREEN D4 CTRL_LED2 56R 0402 R13 GREEN D5 CTRL_LED3 56R 0402 RED LED Kingbright KP2012SURC RS: 466-3829 Farnell: 8529930 LED 0805 Near STOP button RED IDLE state signal IDLE ERROR signal ERROR GREEN LED Kingbright KP2012SURC RS: 466-3778 Farnell: 8529906 LED 0805 GSPG30072014DI1215 DocID026791 Rev 2 9/19 19 Schematic diagrams STEVAL-IME008V1 Figure 9. STEVAL-IME008V1 circuit schematic (9 of 16) GSPG30072014DI1220 U4C FPGA - Bank 2 T15 R15 V16 U16 T13 R13 V15 U15 V14 T14 P12 N12 V13 U13 N11 M11 T11 R11 V12 T12 P11 N10 N9 M10 V11 U11 T10 R10 V10 U10 T8 R8 V9 T9 N8 M8 V8 U8 V7 U7 P8 N7 V6 T6 T7 R7 P7 N6 T5 R5 V5 U5 T3 R3 V4 T4 P6 N5 V3 U3 FPGA_MODE0 CCLK FPGA_SPI_MOSI FPGA_SPI_MISO1 FPGA_SPI_MISO3 FPGA_SPI_MISO2 FPGA_MODE1 TP2 TEST POINT 1 IO_2_L01N_M0_CMPMISO IO_2_L01P_CCLK IO_2_L02N_CMPMOSI IO_2_L02P_CMPCLK IO_2_L03N_MOSI_CSI_B_MISO0 IO_2_L03P_D0_DIN_MISO_MISO1 IO_2_L05N IO_2_L05P IO_2_L12N_D2_MISO3 IO_2_L12P_D1_MISO2 IO_2_L13N_D10 IO_2_L13P_M1 IO_2_L14N_D12 IO_2_L14P_D11 IO_2_L15N IO_2_L15P IO_2_L16N_VREF IO_2_L16P IO_2_L19N IO_2_L19P IO_2_L20N IO_2_L20P IO_2_L22N IO_2_L22P IO_2_L23N IO_2_L23P IO_2_L29N_GCLK2 IO_2_L29P_GCLK3 IO_2_L30N_GCLK0_USERCCLK IO_2_L30P_GCLK1_D13 IO_2_L31N_GCLK30_D15 IO_2_L31P_GCLK31_D14 IO_2_L32N_GCLK28 IO_2_L32P_GCLK29 IO_2_L40N IO_2_L40P IO_2_L41N_VREF IO_2_L41P IO_2_L43N IO_2_L43P IO_2_L44N IO_2_L44P IO_2_L45N IO_2_L45P IO_2_L46N IO_2_L46P IO_2_L47N IO_2_L47P IO_2_L48N_RDWR_B_VREF IO_2_L48P_D7 IO_2_L49N_D4 IO_2_L49P_D3 IO_2_L62N_D6 IO_2_L62P_D5 IO_2_L63N IO_2_L63P IO_2_L64N_D9 IO_2_L64P_D8 IO_2_L65N_CSO_B IO_2_L65P_INIT_B PROG_LED14 PROG_LED15 MCU_FPGA_GPIO6 MCU_FPGA_GPIO7 MCU_FPGA_GPIO4 MCU_FPGA_GPIO5 PROG_LED12 PROG_LED13 MCU_FPGA_GPIO2 MCU_FPGA_GPIO3 MCU_FPGA_GPIO0 MCU_FPGA_GPIO1 PROG_LED10 PROG_LED11 PROG_LED2 PROG_LED3 PROG_LED6 PROG_LED7 PROG_LED0 PROG_LED1 PROG_LED4 PROG_LED5 PROG_LED8 PROG_LED9 FPGA_SPI_SEL FPGA_INIT_B XC6SLX16-2CSG324C MCU_FPGA_GPIO0 MCU_FPGA_GPIO1 MCU_FPGA_GPIO2 MCU_FPGA_GPIO3 MCU_FPGA_GPIO4 MCU_FPGA_GPIO5 MCU_FPGA_GPIO6 MCU_FPGA_GPIO7 MCU_FPGA_GPIO[0:7] 10/19 DocID026791 Rev 2 MCU_FPGA_GPIO[0:7] STEVAL-IME008V1 Schematic diagrams Figure 10. STEVAL-IME008V1 circuit schematic (10 of 16) FPGA CONFIGURATION +VFPGA_IO_3V3 R16 10K 0402 R17 2K43 0402 R18 2K43 0402 DNP FPGA_INIT_B FPGA_MODE0 FPGA_MODE1 MCU_FPGA_INIT_B MCU_FPGA_MODE1 R21 2K43 0402 DNP R22 2K43 0402 Configuration mode selection: FPGA_MODE0 = Parallel (Low) or Serial (High) FPGA_MODE1 = Master (Low) or Slave (High) When FPGA_INIT_B (bidirectional open-drain) is Low the configuration memory is being cleared. When held Low, the start of configuration is delayed. During configuration, a Low on this output indicates that a configuration data error has occurred. SPI FLASH CTRL SIGNALS Place R38 close to the FPGA device R38 33R2 0402 SPI EXTERNAL PROGRAMMING HEADER CCLK FPGA_SPI_MISO1 FPGA_SPI_MOSI FPGA_SPI_SEL FPGA_SPI_MISO2 FPGA_SPI_MISO3 FPGA_SPI_CCLK FPGA_SPI_MISO1 FPGA_SPI_MOSI FPGA_SPI_SEL FPGA_SPI_MISO2 FPGA_SPI_MISO3 MCU_FPGA_PROG +VFPGA_IO_3V3 TO CORRECT J10 1 2 3 4 5 6 7 8 9 10 R39 NA 0402 C33 10uF 10V 0805 CON10 R127 56 EXT SPI FLASH Place D29 close to J10 C34 100nF R40 NA 0402 D29 GREEN C33 Details: TDK (C2012X7R1A106K) - DIGIKEY (445-6857-2-ND) Dimension 0805 - EIA 2012 GSPG30072014DI1230 DocID026791 Rev 2 11/19 19 Schematic diagrams STEVAL-IME008V1 Figure 11. STEVAL-IME008V1 circuit schematic (11 of 16) PROGRAM SELECTOR LEDS PROG 0 R14 PROG 8 R15 D6 PROG_LED0 D7 PROG_LED8 68R 0402 YELLOW 68R 0402 PROG 9 PROG 1 R19 R20 D8 PROG_LED1 YELLOW D9 PROG_LED9 68R 0402 YELLOW 68R 0402 PROG 10 PROG 2 R23 YELLOW R24 D10 D11 PROG_LED10 PROG_LED2 68R 0402 YELLOW 68R 0402 PROG 11 PROG 3 R25 R26 D12 PROG_LED3 YELLOW D13 PROG_LED11 68R 0402 YELLOW 68R 0402 PROG 12 PROG 4 R27 YELLOW R28 D14 D15 PROG_LED12 PROG_LED4 68R 0402 68R 0402 YELLOW PROG 13 PROG 5 R29 YELLOW R30 D16 D17 PROG_LED13 PROG_LED5 68R 0402 YELLOW 68R 0402 PROG 6 R31 PROG 14 R32 D18 PROG_LED6 YELLOW D19 PROG_LED14 68R 0402 YELLOW 68R 0402 PROG 7 R33 PROG 15 R34 D20 PROG_LED7 YELLOW D21 PROG_LED15 68R 0402 YELLOW 68R 0402 YELLOW Kingbright KP-3216SYC RS: 466-3942 LED 0805 GSPG30072014DI1235 12/19 DocID026791 Rev 2 8 7 6 5 1 2 3 4 CON14A Xilinx Parallel IV Connector 2.0mm 7x2 shrouded header SUSPEND SW PUSHBUTTON-DPST RS (378-6527) FPGA PROG RST1 1 2 3 R49 10K 0402 JUMPER J13 2 4 1 FPGA_PROG To be placed near U3 C73 100nF 74LX1G08CTR 4 A17 B18 D16 D15 FPGA_CMP_CS_B P13 V2 FPGA_PROG FPGA_SUSPEND R16 V17 FPGA_DONE FPGA_TCK FPGA_TMS FPGA_TDO FPGA_TDI Jumper J13 used to prevent FPGA from programming from configuration source. Set 1:2 to disable FPGA programming. Open (default) to enable FPGA programming. 2 U7 +VFPGA_IO_3V3 74V1G32CTR U6 10K 0402 R45 NOT ASSEMBLY R43 49R 0402 NOT ASSEMBLY R44 49R 0402 NOT ASSEMBLY R42 49R 0402 NOT ASSEMBLY R41 49R 0402 RESDIP4X1206 RN1 RESISTOR DIP 4 4-Resistor Array 3.2x1.6mm Not Assembly R50 10K 0402 10K 0402 R48 1 R46 10K 0402 FPGA PROG DISABLE 1 2 C62 100nF Header 3 J12 MCU_FPGA_PROG PROGRAM_B Jumper J12 1:2 to force FPGA into suspend mode. 2:3 (Default) to allow MCU to control FPGA suspend mode. MCU_FPGA_SUSPEND To be placed near U6 +VFPGA_IO_3V3 SUSPEND & CMPCS_B 1 3 5 7 9 11 13 J11 NOT ASSEMBLY 2 4 6 8 10 12 14 FPGA JTAG D22 STTH102A NOT ASSEMBLY 5 3 CMPCS_B_2 PROGRAM_B_2 SUSPEND DONE_2 TCK TMS TDO TDI U4E XC6SLX16-2CSG324C 0.22uF 6.3V 0402 C44 FPGA - Power & Configuration DONE FPGA_MCU_DONE DONE FPGA_DONE R52 330 0402 +VFPGA_IO_3V3 Q1 2N7002 D23 GREEN R51 56R 0805 R47 0 FPGA BANK 3 NOT USED E2 G4 J2 J5 M4 R2 P9 R12 R6 U14 U4 U9 E17 G15 J14 J17 M15 R17 B10 B15 B5 D13 D7 E10 C66 C68 0.22uF 6.3V 0402 0.22uF 6.3V 0402 0.22uF 6.3V 0402 0.22uF 6.3V 0402 C72 C69 +VFPGA_IO_3V3 0.22uF 6.3V 0402 4.7uF 6.3V 0603 C71 4.7uF 6.3V 0603 C67 0.22uF 6.3V 0402 C65 C61 +VFPGA_IO_3V3 4.7uF 6.3V 0603 C70 100uF 6.3V 1206 0.22uF 6.3V 0402 0.22uF 6.3V 0402 C57 C54 C60 0.22uF 6.3V 0402 C63 0.22uF 6.3V 0402 4.7uF 6.3V 0603 C64 C59 100uF 6.3V 1206 0.22uF 6.3V 0402 C58 0.22uF 6.3V 0402 C56 4.7uF 6.3V 0603 100uF 6.3V 1206 C55 C53 C52 4.7uF 6.3V 0603 C51 +VFPGA_IO_3V3 C35, C40, C51, C58, C66 Details C36, C37, C38, C41, C42, C52, C53, C59, C60, C67, C68 Details Murata (GRM31CR60J107ME39L) - Digikey (490-4539-1-NDT )DK (C1608X5R0J475K) - Digikey (445-5178-2-ND) Dimension 0603 - EIA 1608 Dimension 1206 - EIA 3216 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 XC6SLX16-3CSG324C 0.22uF 6.3V 0402 C43 +VFPGA_CORE_1V2 0.22uF 6.3V 0402 0.22uF 6.3V 0402 0.22uF 6.3V 0402 0.22uF 6.3V 0402 0.22uF 6.3V 0402 0.22uF 6.3V 0402 C50 C49 C42 C48 C47 C46 C45 C41 4.7uF 6.3V 0603 100uF 6.3V 1206 4.7uF 6.3V 0603 4.7uF 6.3V 0603 C40 C39 0.22uF 6.3V 0402 C38 +VFPGA_IO_3V3 4.7uF 6.3V 0603 100uF 6.3V 1206 +VFPGA_IO_3V3 +VFPGA_CORE_1V2 C37 C36 4.7uF 6.3V 0603 C35 +VFPGA_IO_3V3 +VFPGA_CORE_1V2 B1 B17 E14 E5 E9 G10 J12 K7 M9 P10 P14 P5 VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX G7 H11 H9 J10 J8 K11 K9 L10 L8 M12 M7 VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND +VFPGA_IO_3V3 5 3 DocID026791 Rev 2 A18 B13 C3 D10 D5 B7 C16 G17 G2 G5 H10 H8 J11 J15 J4 E15 G12 K8 L11 L9 M17 M2 M6 N13 R1 R14 R18 R4 R9 T16 U12 U6 V1 V18 K10 J9 A1 FPGA JTAG STEVAL-IME008V1 Schematic diagrams Figure 12. STEVAL-IME008V1 circuit schematic (12 of 16) GSPG30072014DI1240 13/19 19 CW CK CW CK THSD_EN SEL XDCR_4 BNC IN6_1 Jch4 Jch3 XDCR_3 BNC Jch2 IN6_0 IN5_1 IN5_0 IN4_1 IN4_0 IN3_1 IN3_0 IN2_1 IN2_0 XDCR_2 BNC IN1_1 BNC XDCR_1 Jch1 IN1_0 HVM1 HVM0 HVM_CW DVDD VDDP VDDM 1 1 1 1 J16, J17, J22, J23, J25, J26, J29 and J30 Details Tyco Electronics (1-1337482-0) - RS (420-5401) THSD_EN SEL IN4_2 IN4_1 IN4_0 IN3_2 IN3_1 IN3_0 IN2_2 IN2_1 IN2_0 IN1_2 IN1_1 IN1_0 HVM1 HVM0 HVM_CW DVDD VDDP VDDM HVP1 HVP0 HVP_CW HVP1 HVP0 HVP_CW HVM0 HVP0 C77, C80, C111, C112 Details DigiKey (490-1462-2-ND) Murata (GRM188R72A271KA01D) 220n CX1 C113 270p 100V 0603 100 R53 7 8 9 220n HVM1 HVM_CW 10 220n 220n 220n C88 CX2 CX4 C86 J28 B2S 100 R62 D35 DFLS1200 5 220n CX3 C112 270p 100V 0603 J31 B2S D36 DFLS1200 12 11 6 4 220n HVM0 C90 3 2 1 U8 DFLS1200 D31 J21 B2S R55 100 270p 100V 0603 C80 J20 B2S D32 DFLS1200 DFLS1200 D33 D38 DFLS1200 220n CX5 DFLS1200 D37 220n 220n CX6 C93 220n C91 D34 DFLS1200 HVM0 HVP0 2 1 2 1 C77 1 Jlch2 LVOUT_2 BNC 1 2 LVOUT_1 Jlch1 BNC Jlch3 BNC LVOUT_3 XDCR_4 XDCR_3 HVM_CW HVM1 HVM1 HVM1 HVM0 HVM0 HVM0 GND_PWR XDCR_2 XDCR_1 1 47 J16, J17, J22, J23, J25, J26, J29 and J30 Details Tyco Electronics (1-1337482-0) - RS (420-5401) 2 2 1 1 1 B2S J14 B2S J15 STHV749 B2S J16 B2S J17 LVOUT_4 Jlch4 BNC 1 1 2 2 40 D1, D2, D3 ,D4, D5, D6, D7, D8 diode DFLS1200 rs-code 708-2324 1 2 2 2 R54 100 13 C92 C76 2 2 C75 C74 IN2_2 IN2_1 IN2_0 IN1_2 IN1_1 IN1_0 CW 25 26 27 20p 0805 20p 0805 SEL VDDM 28 HVP1 29 30 31 CK J25 CON3 CX12 C97 220n C83 C87 220n 220n C85 C101 220n CX11 220n 220n 220n HVP_CW CX7 220n DVDD 32 HVP0 33 34 35 36 STHV749 IN4_2 IN4_1 IN4_0 IN3_2 IN3_1 IN3_0 VDDP VDDP AGND VDDM HVP1 HVP1 HVP1 HVP0 HVP0 HVP0 HVP_CW DGND DVDD 20p 0805 20p 0805 1 2 3 270p 100V 0603 1 2 48 GND_PWR GND_PWR 46 LVOUT_2 LVOUT_3 14 LVOUT_1 LVOUT_4 15 45 GND_PWR 43 IN2_1 44 17 GND_PWR 16 IN2_2 IN3_0 42 19 IN3_2 2 2 20 IN3_1 18 IN2_0 41 IN1_2 39 IN1_1 21 IN4_1 22 IN4_0 37 IN1_0 IN4_2 38 CK CW THSD 23 VDDP 24 DocID026791 Rev 2 220n CX9 C102 220n CX8 220n C89 220n CX10 220n 220n C95 CK TP3 TEST POINT 1 14/19 2 R59 100k THSD R58 10k THSD_EN DVDD 1 2 3 CON3 J24 THSD Schematic diagrams STEVAL-IME008V1 Figure 13. STEVAL-IME008V1 circuit schematic (13 of 16) GSPG30072014DI1245 STEVAL-IME008V1 Schematic diagrams Figure 14. STEVAL-IME008V1 circuit schematic (14 of 16) OPTIONAL FPGA I/O STM32_GPIO_0 STM32_GPIO_1 STM32_GPIO_2 STM32_GPIO_3 STM32_GPIO_4 STM32_GPIO_5 STM32_GPIO_6 STM32_GPIO_7 FPGA_GPIO0 FPGA_GPIO1 FPGA_GPIO2 FPGA_GPIO3 FPGA_GPIO4 FPGA_GPIO5 FPGA_GPIO6 FPGA_GPIO7 0R - N/A 0R - N/A 0R - N/A 0R - N/A 0R - N/A 0R - N/A 0R - N/A 0R - N/A R69 R70 R71 R72 R73 R74 R75 R80 FPGA_GPIO[0:7] FPGA_GPIO[0:7] OPTIONAL FPGA CONFIGURATION SIGNALS STM32_GPIO_8 STM32_GPIO_9 STM32_GPIO_10 STM32_GPIO_11 STM32_GPIO_12 STM32_GPIO_13 STM32_GPIO_14 JTAG/SWD R76 10k JNTRST JTMS JTCK JTDO JTDI RESET# R82 R83 R84 R85 R86 R88 R89 0R - N/A 0R - N/A 0R - N/A 0R - N/A 0R - N/A 0R - N/A 0R - N/A FPGA_MCU_AWAKE FPGA_MCU_DONE MCU_FPGA_OSC_EN MCU_FPGA_INIT_B MCU_FPGA_MODE1 MCU_FPGA_PROG MCU_FPGA_SUSPEND FPGA_MCU_AWAKE FPGA_MCU_DONE MCU_FPGA_OSC_EN MCU_FPGA_INIT_B MCU_FPGA_MODE1 MCU_FPGA_PROG MCU_FPGA_SUSPEND MCU_3V3 R77 10k R78 10k Male Connector 2x5 Pitch 1.27 mm SAMTEC FTSH-105-01-F-D-K R79 10k 2 JP1 JUMPER 1 MCU_3V3 J40 2 4 6 8 10 1 3 5 7 9 SWD/JTAG R87 10k MCU JTAG GSPG30072014DI1250 DocID026791 Rev 2 15/19 19 DocID026791 Rev 2 FLASH_DQ0 FLASH_C FLASH_nS FLASH_DQ2 FLASH_DQ3 FLASH_DQ0 FLASH_C FLASH_nS FLASH_DQ2 FLASH_DQ3 SPI FLASH R130 4k7 R129 4k7 5 6 1 3 7 2 FLASH_DQ1 C123 1uF 6.3V C122 100nF R66 4K7 MCU_3V3 USB_DISCONNECT USB_DM USB_DP FLASH_DQ1 56 N25Q032xSC D30 RED R128 INT SPI FLASH R67 4K7 VDDA BOOT0 BOOT1 RESET# MCU_3V3 FLASH_3V3 9 44 20 7 3 4 2 STM32F103C8T6 VDDA BOOT0 PB2-BOOT1 NRST PC14-OSC32_IN PC15-OSC32_OUT PC13-Tamper-RTC PA0-WKUP PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 MCU 10 STM32_GPIO_0 11 STM32_GPIO_1 12 STM32_GPIO_2 13 STM32_GPIO_3 14 STM32_GPIO_4 15 STM32_GPIO_5 16 STM32_GPIO_6 17 STM32_GPIO_7 29 STM32_GPIO_8 30 STM32_GPIO_9 USB_DISCONNECT31 32 DM_STM32 33 DP_STM32 Use J38 to enable/disable power for SPI flash device. J38 must be open when using external spi flash device on connecto J10. Default value closed. FLASH DISABLE DQ0 DQ1 C nS nW/Vpp/DQ2 nHOLD/DQ3 U9 0R - N/A R64 2 1 J38 C123 Details: Digikey (445-4998-2-ND) - TDK (C1005X5R0J105K) Package 0402 R131 C116 100nF 4k7 FLASH_3V3 8 VCC VSS 4 MCU_3V3 48 36 24 1 VDD_3 VDD_2 VDD_1 VBAT VSSA VSS_1 VSS_2 VSS_3 16/19 8 23 35 47 MCU_3V3 USER_LED1 USER_LED2 STM32_GPIO_10 STM32_GPIO_11 STM32_GPIO_12 STM32_GPIO_13 STM32_GPIO_14 FLASH_DQ3 FLASH_DQ2 FLASH_nS FLASH_C FLASH_DQ1 FLASH_DQ0 OSCIN OSCOUT 5 6 JNTRST JTDO JTDI JTCK JTMS C120 100nF MCU_3V3 18 19 41 42 43 45 46 21 22 25 26 27 28 U10 40 39 38 37 34 STM32F103 PD0 OSC_IN PD1 OSC_OUT PB0 PB1 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB4 JNTRST PB3 JTDO PA15 JTDI PA14 JTCK PA13 JTMS C119 100nF Place near MCU C118 100nF FLASH_3V3 C121 100nF Schematic diagrams STEVAL-IME008V1 Figure 15. STEVAL-IME008V1 circuit schematic (15 of 16) GSPG30072014DI1255 STEVAL-IME008V1 Schematic diagrams Figure 16. STEVAL-IME008V1 circuit schematic (16 of 16) MCU_3V3 R65 10K RESET# C117 100nF RST2 MCU RESET SW PUSHBUTTON-DPST Not Assembly RS (505-9186) C&K (Y78B22110FP) OSCILLATOR Y1 OSCIN OSCOUT 8MHZ OSC 8MHz Murata (CSTCE8M00G55-R0) DigiKey (490-1195-1-ND) RS: 283-961 Farnell: 1615352 DOWNLOAD D24 R68 56R USER_LED1 RED Kingbright KP2012SURC RS: 466-3829 Farnell: 8529930 LED 0805 FLASH READY D25 R81 56R USER_LED2 RED Kingbright KP2012SURC RS: 466-3829 Farnell: 8529930 LED 0805 GSPG30072014DI1300 DocID026791 Rev 2 17/19 19 Revision history 2 STEVAL-IME008V1 Revision history Table 1. Document revision history 18/19 Date Revision Changes 06-Aug-2014 1 Initial release. 06-Aug-2015 2 Updated title on the cover page. DocID026791 Rev 2 STEVAL-IME008V1 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved DocID026791 Rev 2 19/19 19