STEVAL-ISA051V2
Complete DDR2/3 memory power supply controller
evaluation board based on the PM6670AS
Data Brief
Features
■
4.5 V to 36 V input voltage range
■
0.9 V, ±1% voltage reference
■
1.8 V (DDR2) or 1.5 V (DDR3) fixed output
voltages
■
0.9 V to 2.6 V adjustable output voltage
■
1.237 V ±1% reference voltage available
■
Very fast load transient response using
constant on-time loop control
■
No RSENSE current sensing using the RDS(on)
of the low-side MOSFETs
■
Negative current limit
■
Latched OVP, UVP and thermal shutdown
■
Fixed 3 ms soft-start
■
Selectable pulse-skipping at light load
■
Selectable no-audible (33 kHz) pulse-skip
mode
■
All ceramic output capacitors application
supported
■
Output voltage ripple compensation
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STEVAL-ISA051V2
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The device is fully compliant with system sleep
states S3 and S4/S5, providing LDO output high
impedance in suspend-to-RAM and tracking
discharge of all outputs in suspend-to-disk.
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Description
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This evaluation board based on the PM6670AS
device is a complete DDR2/3 power supply
regulator for portable applications designed to
meet JEDEC specifications. It integrates a
constant on-time (COT) buck controller, a 2 Apk
sink/source low dropout regulator and a 15 mA
low noise buffered reference.
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The COT architecture assures fast transient
response supporting both polymeric and ceramic
output capacitors. An embedded integrator
control loop compensates the DC voltage error
due to the output ripple. The 2 Apk sink/source
linear regulator provides the memory termination
voltage with fast load transient response.
March 2008
Rev 1
For further information contact your local STMicroelectronics sales office.
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www.st.com
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AGND
AGND
VTT
TTREF
EF
VTT
LDOIN
VCC
CCGND
J11
J10
J8
J7
J6
J9
1
1
1
1
1
1
1
2
0
0
C8
33n
0
C5
1u
1
2
1
2
10
10u
C6
1
0
C7
DDR
DRSEL
JP1
10
10u
0
R7
3R9
2
C9
100n
10
C10
10u
1
1
0
C19
10u
C20
1
2
0
R8
27k
27
R9
18
18k
1
2
3
4
5
6
25
R10
0
MODE
JP3
18
17
16
15
14
13
2
R3 1k5
JP2
P2
DSCG
VCC
1
D1
BA
BAT41J
C12
100n
VCC
VTTGND
VCC
VTTSNS
LGATE
DDRSEL
DDR
SEL
PGND
VTTREF
EF PM66
PG
6670AS
AS
SGND
S3
AVCC
S5
THPD
PD
U1
0
C11
10u
1
R2
18k
18
0
C21
100p
100
1
2
0
1
0
1
C14
00n
100
C13
100
00n
2
VCC
1
2
1
2
1
2
2
1
24
23
22
21
20
19
VTT
LDOIN
BOOT
HGATE
PHASE
ASE
CSNS
VREF
EF
VOSC
SC
VSNS
VS
MODE
COMP
DSCG
7
8
9
10
11
12
2
2
4
6
1
3
5
2
1
2
1
2
2
4
6
1
3
5
2
1
1
C22
100p
4
3
0
1
2
R13
10
100k
10
100k
2
R12
1
SW1
VCC
10
100k
2
R11
1
0
R17
0
2
Q2
STS7NF60L
4
4
Q1
60L
STS5NF60
2
R1 330k
33
R4 3R3
1
5
6
7
8
1
2
3
5
6
7
8
0
1
2
3
J5
1
2
C17
0
0
1
2
D2
C1
10u
2
680
80p
C16
C18
1n
R16
4R7
R14
JP5
TP1
GND
ND_TP
INT_CER
u
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1
0
1
7.5k
L1
1
2
VCC
STPS
PS1L
1L60A
2
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1
1
2
1
2/4
2
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0
2
2
47n
1
C15
R15 6.8k
1u
C2
10u
R6
0
1
2
P
e
220
20u
C3
1
2
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u
)
(s
220
20u
C4
1
2
D3
1
1
1
1
PG
J4
PGND
J3
VDD
DDQ
J2
VIN
J1
Figure 1.
STPS
PS1L
1L60A
1
2
Circuit schematic
STEVAL-ISA051V2
Circuit schematic
Schematic
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STEVAL-ISA051V2
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Revision history
Revision history
Table 1.
Document revision history
Date
Revision
03-Mar-2008
1
Changes
Initial release.
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STEVAL-ISA051V2
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