STEVAL-ISA110V1
12 V/12 W wide-range non-isolated flyback based on the
VIPER26LN
Data brief
Features
■
Universal input mains range:
– input voltage 90 - 264 VAC
– frequency 45 - 65 Hz
■
Single output voltage: 12 V @ 1 A continuous
operation
■
Standby mains consumption: < 30 mW @ 265
VAC
■
Average efficiency: > 85%
■
Fully protected against faults (overload,
feedback disconnection and overheating)
■
EMI: according to EN55022-Class-B
STEVAL-ISA110V1
Description
The STEVAL-ISA110V1 demonstration board is a
12 V-1 A power supply set in non-isolated flyback
topology using the VIPER26LN, a new offline
high-voltage converter by STMicroelectronics.
The features of the device include an 800 V
avalanche-rugged power section, PWM operation
at 60 kHz with frequency jittering for lower EMI,
current limiting with adjustable set point, onboard
soft-start, a safe auto-restart after a fault
condition, and low standby power.
Protection features include thermal shutdown with
hysteresis, delayed overload protection, and open
loop failure protection.
February 2013
Doc ID 024123 Rev 1
For further information contact your local STMicroelectronics sales office.
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www.st.com
10
Adapter features
1
STEVAL-ISA110V1
Adapter features
The electrical specifications of the demonstration board are listed in Table 1.
Table 1.
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Electrical specifications
Symbol
Parameter
Value
VIN
Input voltage range
90 VAC; 265 VAC
VOUT
Output voltage
12 V
IOUT
Max. output current
1A
∆VOUT_LF
Precision of output regulation
±5%
∆VOUT_HF
High frequency output voltage ripple
50 mV
TAMB
Max. ambient operating temperature
60 °C
Doc ID 024123 Rev 1
C6
F
Doc ID 024123 Rev 1
C4
C5
R7
C7
C8
COMP
FB
R2
+
LIM
R5
CONTROL
VDD
C1
D2
C2
GND
DRAIN
+
D1
D4
J2
T1
VIPER26
IC1
2
1
3
C9
5
8,9
6,7
D6
D3
C10
+
C11
+
L1
C12
+
GROUND
VOUT
Application schematic - complete
+
+
L2
Figure 1.
R4b
t
J1
-
D0
Schematic diagrams
R4a
R3
NTC
2
D5
R1
AC IN
AC IN
STEVAL-ISA110V1
Schematic diagrams
AM11547v1
3/10
Schematic diagrams
STEVAL-ISA110V1
3
GND
R5
R7
C7
C6
R4b
R3
AC IN
F
R4a
C4
+
C5
-
NTC
t
AC IN
C8
COMP
LIM
CONTROL
D0
+
FB
C1
VDD
+
L2
C2
+
DRAIN
D4
D1
1
3
5
T2
D6
VIPER26
8,9
6,7
D3
C10
+
C11
+
VOUT
GROUND
Application schematic - simplified for VOUT ≥12 V
Figure 2.
AM11548v1
4/10
Doc ID 024123 Rev 1
STEVAL-ISA110V1
Bill of material
3
Bill of material
Table 2.
Bill of material (relevant to schematic in Figure 2 )
Reference
Part
NTC
2.2 Ω NTC
NTC thermistor
F
T2A 250 V
2 A, 250 Vac fuse, TR5 series
Wickmann
C1
10 μF, 400 V NHG series electrolytic capacitor
Panasonic
C2
22 μF, 35 V SMG series electrolytic capacitor
Panasonic
C4
2.2 μF, 63 V electrolytic capacitor
C5
100 nF, 50 V ceramic capacitor
C6
1 nF, 50 V ceramic capacitor
C7
47 nF, 50 V ceramic capacitor
C8
2.2 nF, 50 V ceramic capacitor
C9
Description
Manufacturer
EPCOS
Not mounted
C10
1000 μF, 16 V ultra low ESR electrolytic capacitor ZL series
Rubycon
C11
680 μF, 16 V ultra low ESR electrolytic capacitor ZL series
Rubycon
C12
Not mounted
D0
DF06M
D1
STTH1L06
D2
Not mounted
D3
1 A - 600 V diode bridge
Vishay
1 A - 600 V ultrafast diode
ST
STPS3150
3 A-150 V power Schottky (output diode)
ST
D4
1.5KE300A
Transil
ST
D5
Not mounted
D6
1N4148
R1
Not mounted
R2
Not mounted
Small signal diode
R3
47 kΩ 1% 1/4 W resistor
R4a
15 kΩ 1% 1/4 W resistor
R4b
2.7 kΩ 1% 1/4 W resistor
R5
33 kΩ 1/4 W resistor
R7
3.3 kΩ 1/4 W resistor
L1
Short-circuit
L2
RFB0807-102
T1
1715.0049
IC1
VIPER26LN
High-voltage 60 kHz PWM
J1
Not mounted
Jumper
J2
Short-circuit
Jumper
Input filter inductor (L = 1 mH, ISAT = 0.3 A; DCR max. = 3.4 Ω)
60 kHz switch mode transformer
Doc ID 024123 Rev 1
Fairchild
Coilcraft
Magnetica
ST
5/10
Line/load regulation and output voltage ripple
4
STEVAL-ISA110V1
Line/load regulation and output voltage ripple
The output voltage of the board has been measured in different line and load conditions:
Line regulation
Figure 4.
12.3
12.3
12.2
12.2
0
12.1
25%
50%
Vout[V]
Vout[V]
Figure 3.
75%
12
Load regulation
90
12.1
115
230
12
265
100%
11.9
11.9
80
105
130
155
180
205
230
0
255
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1.1
Iout[A]
Vin[V]
AM11557v1
Figure 5.
1
Efficiency vs. VIN
AM11558v1
Figure 6.
Efficiency vs. load
100
89
95
87
85
85
eff [%]
eff [%]
90
80
83
90
25%
75
50%
230
75%
70
115
81
79
265
100%
77
65
60
75
80
110
140
170
200
230
260
0.2
Vin[Vac]
0.6
0.8
1
Iout[A]
AM11565v1
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0.4
Doc ID 024123 Rev 1
AM11566v1
STEVAL-ISA110V1
Figure 7.
Line/load regulation and output voltage ripple
Active mode efficiency vs. VIN
Figure 8.
Input voltage averaged efficiency
vs. load
100
89
95
87
90
85
80
75
eff [%]
eff [%]
eff [%]
85
83
81
70
79
65
77
75
60
80
110
140
170
200
230
0
260
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Vin[V]
AM11567v1
Figure 9.
1.1
AM11568v1
PIN vs. VIN @ no load and light load Figure 10. Efficiency @ PIN = 1 W
200
90
0
175
85
25mW
150
80
50mW
125
75
eff [%]
Pin [mW]
1
Iout[A]
100
75
70
65
50
60
25
55
0
80
105
130
155
180
205
230
255
Vin[V]
50
80
110
140
170
200
230
260
Vin[V]
AM11570v1
Doc ID 024123 Rev 1
AM11571v1
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Board layout
5
STEVAL-ISA110V1
Board layout
Figure 11. Bottom layer & top overlay
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Doc ID 024123 Rev 1
STEVAL-ISA110V1
6
Revision history
Revision history
Table 3.
Document revision history
Date
Revision
11-Feb-2013
1
Changes
Initial release.
Doc ID 024123 Rev 1
9/10
STEVAL-ISA110V1
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