STEVAL-PSQ001V1

STEVAL-PSQ001V1 Power management for CPU, FPGA and memory based on the PM6680A Data Brief Features ■ Input: 5 - 36 VDC, surge protection ■ Output voltages: – Output1 (Vcore) selectable from: 0.9, 1.0, 1.2, 1.5, 1.8 or 2.5 V, 4 A continuously (6 A peak), tolerance: 3% – Output2 (Vi/o) selectable from: 1.0, 1.2, 1.5, 1.8, 2.5 V or 3.3 V, 2 A continuously (3 A peak), tolerance: 3% – Output3 Vsys: 3.3 V 0.4 A (0.8 A peak), tolerance: 4% – Output3 Vaux: 2.5 V, 0.4 A, tolerance: 2% ■ Analog 5: 5 V, 0.8 A, tolerance: 4% ■ Analog 3.3 V: 3.3 V, 0.15 A, tolerance: 2% Description ) s ( ct u d o r P e t e l o )- s ( t c The main purpose of this evaluation board is to show basic principles used for design of the power supply and to give users a working prototype for testing and daily use. The trend in recent years in the supply of MCUs, CPUs, memories, FPGAs etc. is to reduce the supply voltage, increase supply current and provide various voltage levels for different devices in one platform. A typical example of this is the FPGA. FPGAs contain core parts which operate with low level voltage, interface parts placed between the core and the output, system parts, etc. It is important to note that each family of parts has a slightly different voltage level and the trend is toward decreasing voltage for each new family. The lowest operating voltage currently is 1 V, and this can be expected to drop to 0.9 V or 0.8 V in the near future. The situation is similar with other parts of digital solutions. Typically, the main CPU, memory, and interfaces require different supply voltage levels. Low operating voltage also bring another challenge - transient. Digital devices are typically sensitive to voltage level. If voltage drops below or crosses over established limits, the device is u d o r P e t e l o s b O February 2008 s b O reset. This limit is typically ± 3 or 5 %. On the other hand, digital device consumption can change very fast (approx. several amps in several hundred nanoseconds). The power supply must be capable of reacting very quickly with a minimum of over/under voltage, especially in cases where very low voltage output is required. There is additional stress placed on power supplies in digital applications for industrial use. The industrial standard bus is 24 V, but this voltage fluctuates and the maximum required input voltage level can be up to 36 V. Additional surge protection is also mandatory for power supply input in industrial applications. The purpose of this evaluation board is to address all of required parameters outlined above. This means satisfying industrial input requirements (operating voltage of up to 36 V) and generating several output voltages for middle power applications (up to several amps). The main output voltage level can be set easily. Rev 1 For further information contact your local STMicroelectronics sales office. STEVAL-PSQ001V1 1/4 www.st.com 4 GND io S32 S33 FB1 S8 0.9V S9 1V R107 9k1 R101 1k Vio 0.9 - 2.5V/2A S34 S35 Input 1 R108 820k R102 R10 2 2k S10 1.2V R103 3k S11 1.5V R1043k R10 3k S12 1.8V R105 R106 7k5 110k C22 330u/6.3V C18 10u/50V Vin R11 300R C21 100pF C20 560pF L3 4.7uH/3A C35 D8 STPS2L40 R40 R4 0 10R 100n R39 R3 9 10R D1 SMAJ33A 1 8 7 3 6 5 4V7 R24 10R R23 10R R2 VLDO R28 R2 8 10k 2 4 D10 C36 100pF R29 100k Vin VLDO STS4DNF60 Q1 C1 47uF/50V Vin D3 R10 1k2 C19 100n R34 10k R3 R31 10k R3 5 7 27 2 8 17 12 13 11 R35 51k S3 CH2 EN/SUS 1 R30 R3 0 0R 9 10 C15 470n VLDO C9 220p C3 220p C31 220n R37 R3 7 47R C8 4.7u/35V R25 10R U5 PM6680 PGOOD2 C2 4.7u/35V C14 4.7u/10V 36V D5 L5 10uH/1A 36V BOOT2 SHDN FB2 PGOOD2 COMP2 OUT2 V5SW CSENSE2 LGATE2 PHASE2 HGATE2 3 S4 LDO5 O5 2 3 31 8 C4 22n 8 R1 4k7 4 Vcc COMP S5 LGATE1 PHASE1 HGATE1 BOOT1 D7 OUT1 PGND FB1 SGND1 SGND2 PGOOD1 COMP1 C30 100n SKIP mode S7 R26 10R C17 100n 28 1 16 26 30 29 14 VLDO 20 R19 1k2 15 21 22 23 BAW56/SOT CSENSE1 S6 5k6 R42 C16 3.3u/35V R9 3R3 C10 22n Vin CH1 EN/SUS R36 51k R5 10k 4 U3 L5970AD 5k6 R41 GND GN D U1 L5970AD Vcc COMP SYNC SY 2 FB OUT S1 1 5 Vin D4 STPS2L40 S2 FB OUT Vin D6 STPS2L40 Vsys EN 5 1 Vanalog EN INH J16 2 EN2 4 EN1 25 2 1 19 Vin FSEL FSE L 18 VREF 32 SKIP SK IP 24 NC R33 0R R32 10k VLDO Q3 STS7NF60L R22 R2 2 10R R21 R2 1 10R STS7NF60L C25 100n Q2 D6A STPS1L40M R6 18k L2 15uH/1.5A D4A STPS1L40M R2 120k L1 15uH/1.5A Vin R8 10k R4 5k6 C24 10u/50V FB2R Vaux C11 100u/6V C5 47uF/10V C27 100pF C26 560pF R20 300R 100n R38 10R R38 3.3uH/6A L4 C34 R27 10R R27 STPS2L40 D9 C23 10u/50V R7 240k R3 20k C28 330u/6.3V C29 330u/6.3V r P e 3 t e l o s b O Vcc SYNC SY 2 VREF 6 VREF 6 3 INH 7 GND 7 2/4 3 s b O t e l o C12 100n C6 100n C32 1n C33 R206 R205 110k 7k5 1n VIN INH 4 R204 3k R20 S17 2.5V 1 C13 10u/4V C7 10u/6V RST R203 3k S16 1.8V MR RSTIN Vcc2 Vcc1 R208 6k8 R207 2k2 R2022k R20 2k S15 1.5V 1 U6 STM6719TEWB6F PGOOD2 3 5 4 6 VOUT OUT U4 KF25_SOIC8 GND BYPASS SHDN IN U2 LK112_33 VLDO 8 5 2 3 1 5 GND GND GND GN GN GND P e 2 3 6 7 d o r t c u ) (s Vss S21 R209 110k GND R201 R20 1 1k S14 1.2V STPS2L40 J15 J1 Reset GND J14 Reset S31 S30 S29 S28 Vcore GND FB2R FB2 Vcore 0.9 - 2.5V/4A S24 S25 S26 S27 S13 1V S23 Vaux 2.5V/400mA Vsys 3.3V/400mA S22 Vsys GND Analog S20 3.3V/150mA Vaux D11 S18 5V/400mA S19 V5V Figure 1. 2 1 6 Circuit schematic STEVAL-PSQ001V1 Circuit schematic Schematic ) s ( ct u d o STEVAL-PSQ001V1 2 Revision history Revision history Table 1. Document revision history Date Revision 18-Feb-2008 1 Changes Initial release. ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O 3/4 STEVAL-PSQ001V1 Please Read Carefully: ) s ( ct Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. u d o All ST products are sold pursuant to ST’s terms and conditions of sale. r P e Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. t e l o No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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