STEVAL-TSP009V2

STEVAL-TSP009V2 Data brief 3.3 V/6 A, synchronous flyback converter, Power Over Ethernet (PoE) - IEEE 802.3at compliant reference design Features • • • IEEE 802.3at compliant PD interface Works with power supplied from Ethernet LAN cables or from local auxiliary sources Line input voltage range: 40 VDC to 60 VDC • Output voltage: 3.35 VDC ± 5% • • • • • Output current: 6 A Peak-to-peak output ripple: < 25 mV Efficiency DC-DC full-load: > 90% Overall peak efficiency: > 87% Transient response ΔVOUTPK-PK to 50% load step: < 250 mV • • ΔV in load line case: < 0.5% RoHs compliant Description The STEVAL-TSP009V2 is a reference design for a PoE+, high-efficiency, 3.3 V - 6 A flyback converter based on the PM8803 PoE controller. Product summary 3.3 V/6 A, synchronous flyback converter, Power STEVALOver Ethernet (PoE) - IEEE TSP009V2 802.3at compliant reference design High efficiency integrated IEEE 802.3at PoE-PD interface and PWM controller type 2 PSE indicator, plus support for forward active clamp topology The PM8803 is a highly integrated device embedding an IEEE802.3at-compliant powered device (PD) interface together with a PWM controller and support for auxiliary sources. The STEVAL-TSP009V2 reference design is based on an isolated flyback CCM converter featuring synchronous rectification with gate driver transformer. PM8803 DB2574 - Rev 2 - May 2019 For further information contact your local STMicroelectronics sales office. www.st.com STEVAL-TSP009V2 Detailed description 1 Detailed description The STEVAL-TSP009V2 reference design for the PM8803 covers a broad range of Power over Ethernet (PoE) applications. The PM8803 is a highly integrated device embedding an IEEE802.3at compliant powered device (PD) interface together with a PWM controller and support for auxiliary sources. Although the PM8803 can be configured to work in several isolated topologies (self-driven or transformer gatedriven), we focus here on a high-efficiency isolated flyback converter topology with synchronous rectification, 3.3 V output voltage and 6 A output current capability. Auxiliary sources can be connected to the reference design on two different input connectors: one input (AUX II) allows prevalence of the auxiliary sources with respect to the PoE, whereas the other input (AUX I) allows the use of a wall adapter with voltage lower than the internal PoE UVLO threshold, while still benefitting from the inherent inrush and DC current limit. The possible configurations supported by the STEVAL-TSP009V2 reference design are: • input diode bridges (four possible options, including active bridges) • optional 4-pair detection circuit, to detect a high power PSE source • optional booster circuit, to increase the max input current over 800 mA • diode or synchronous rectification (four package options for diode and three package options for MOSFET) • primary side snubber (three options including active clamp) • power transformer (three size options for transformer gate-driven solutions and two size options for selfdriven) applications 1.1 Efficiency Figure 1. STEVAL-TSP004V2 reference design: 3.3 VOUT overall and DC-DC efficiency DB2574 - Rev 2 page 2/6 STEVAL-TSP009V2 Schematic diagrams 2 Schematic diagrams Figure 2. STEVAL-TSP009V2 circuit schematic (1 of 2) Chassis Chassis 12 13 1 2 3 4 5 6 7 8 11 14 10 15 R175R 16 9 Chassis 17 8 7 Data and power input 18 J4 DATA OUTPUT 9 0603 9 J3 10 10 T1 1 2 3 4 5 6 7 8 Chassis R275R 0603 6 19 5 20 4 21 R575R 0603 22 3 23 2 1 R10 75R 0603 C5 10nF 10% 0603 100V R11 75R 0603 R12 75R 0603 C6 C7 10nF 10% 10nF 10% 0603 0603 100V 100V 24 ETH1-460 R13 75R 0603 R775R 0603 C9 2.2nF 2KV 1812 1206 C8 10nF 10% 0603 100V R1250R0 TP24 BLACK C12 2.2nF 2KV 1812 Chassis Chassis SP TP22 Red TP2 Red AUX 1 J2 1 2 3 R26 0R01206 D1 R17 POE+F POE+F 0R01206 STTH302S SMC SP C14 1nF 10% 0603 100V D7 STPS2H100A SMA D4 STPS2H100A SMA D8 STPS2H100A SMA D9 STPS2H100A SMA R32 15K 0805 D14 STPS2H100A SMA D17 STPS2H100A SMA D12 STPS2H100A SMA R37 DB2574 - Rev 2 RTN C21 1nF 10% 0603 100V D13 STPS2H100A SMA R43 0R0 1206 TP3 BLACK Auxiliary input frontal or AUXI C18 D11 0.1µF 10% SMAJ58A SMA 0805 100V C16 1nF 10% 0805 100V 0R01206 VSS TP23 BLACK page 3/6 STEVAL-TSP009V2 Schematic diagrams Figure 3. STEVAL-TSP009V2 circuit schematic (2 of 2) 48VAUX2 J1 TP7 Red TP4 Red R49 1206 0R0 1 2 3 D21 1 STTH302S TP9 Red L510uH C22 TBD 2 MSS7341-103ML 2KV 1812 SMC SA C64 R51 15K 0805 2.2 µ 1210 100V C26 33µF - 20% 100V 10x10.2 C28 C29 2.2µ 1210 100V 2.2µ 1210 100V C30 150pF 0805 100V TP5 Red R23 100R 1206 R54 1206 0R0 L6 7 6 1 1 TP6 Red 2 9 10 TP10 Red 8 7 6 5 4 T5 5 D28 R66 10R D52 BAT46J R65 1K C67 C68 22µF 1206 16V 22µF 1206 16V 22µF 1206 16V 22µF 1206 16V 4 C33 C35 22µF 1206 16V 22µF 1206 16V C34 330µF 16V 8x10.2 1 2 D26 C36 0.1µ 1 2 TP12 BLACK Output filter STL66N3LLH5 TP13 Red 10R BAT46J C39 1µF 25V 0603 SOD323 10nF C37 PowerFLAT™ 5x6 R62 C38 R70 10K-1% 1% 3 2 1 C27 Q12 COILCRAFT JA4173 - AL R58 27K J5 R52 1K 0805 0805 POE+F SA R53 1R0 Out det C31 1.5nF R21 220R RTN 1206 R72 120K-1% 1% 0.33µH 2 DO1813-331ML InputFilter TP8 BLACK SOD323 TP14 Red C41 1µF 25V 0603 D32 MM3Z15VT1 SOD323 C40 1µF 25V 0805 RTN D34 COILCRAFT DA2319-AL R64 0R0 ARTN 4 R84 16 R131 R27 SP 15 30R9 1% R0805 14 R95 27K 13 24.9K-1%1% 12 11 VSS MMBT3904LT1 SOT23 Q18 R38 1k C69 10nF R101 24.9K-1% 1% R9 1K 1% R0603 VB DT CS RTN DCCL GAT1 CLS VC SP GAT2 DET ARTN VDD RTN VDD VSS 1 0R0 2 R96 0R0 U3 Fairchild FOD817AS 0.1uF 4 R92 10R 5 TP16 6 TP15 Red D57 7 BAT46J 8 1 3 2 C50 100nF SO8 Q17 BAT46J D40 SOD323 ARTN TP18 Red R107 10K C55 100pF R99 47K D39 510R C54 470p ARTN R1044.7K-1% 47nF C56 BAT46J C59 1µF 25V 0603 R108 R109 0.30 ohm - 1%0.30 ohm - 1% 1206 1206 0805 Power circuit VC TP19 BLACK RTN C61 2.2n 3 2 U4 TS431AILT 5 2KV 1% SOD323 100V TP11 BLACK C48 1uF 25V 0603 R93 510R R94 21K-1% 1% Si4848DY 4 9 C60 1nF R91 10R C49 3.3nF SOD323 R103 C53 1µF 4 R90 750R Red R0805 PM8803 HTSSOP20-LARGE C23 470nF 10% 50V 0603 Q16 MMBT3906LT1 SOT23 R89 4.3K 3 10 D36 BAT46J SOD323 T8 21 C19 10nF FRS SA R83 10K 3 R80 27R 5 6 7 8 17 CTL BAT46J SOD323 0.1µF C45 1 2 3 19 18 T2P ExPad 20 6 RTN U1 T2P C44 1 4 1 R112 NM 1% R111 12.4K-1% 1% SOT23-5 1812 RTN Feedback circuit ARTN R122 0R0 RTN D20 Aux det SA SP JM1 Jumper-doppio U2 3 R45 2 1 JM2 Jumper-doppio VSS 3 24.9K Fairchild FOD817AS 1 4 2 3 R44 1K D44 T2P det TP21 Red Auxiliary present R1173.3K VC T2P U7 Fairchild FOD817AS 1 4 2 3 R119 1K TP20 Red T2P present 1 2 RTN Note for resistors Where not indicated, the body is 0603 and tolerance is 5% Note for capacitors Where not indicated, the body is 0603 and the voltage is 50 V Note for Jumpers JM1 and JM2 Move the short on both jumpers at the same time: - short between pin1 and 2 when using AUX2 input - short between pin2 and 3 when using AUX1 input Note: The ARTN is a dedicated plane of signal ground that is connected to the RTN power ground plane close to pin 4 and 9 of PM8803 DB2574 - Rev 2 page 4/6 STEVAL-TSP009V2 Revision history Table 1. Document revision history Date Version 24-Apr-2015 1 Changes Initial release. Updated title. 07-May-2019 2 Added product summary table. Minor text and formatting changes. DB2574 - Rev 2 page 5/6 STEVAL-TSP009V2 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. 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