STF10NM65N

STD10NM65N Datasheet N-channel 650 V, 0.43 Ω typ., 9 A MDmesh™ II Power MOSFET in a DPAK package Features TAB Order code 2 3 1 STD10NM65N DPAK • • • D(2, TAB) VDS @ Tjmax. 710 V RDS(on) max. ID 0.48 Ω 9A 100% avalanche tested Low input capacitance and gate charge Low gate input resistance Applications G(1) • S(3) AM01475v1_noZen Switching applications Description This device is an N-channel Power MOSFET developed using the second generation of MDmesh™ technology. This revolutionary Power MOSFET associates a vertical structure to the company’s strip layout to yield one of the world’s lowest on-resistance and gate charge. It is therefore suitable for the most demanding high efficiency converters. Product status STD10NM65N Product summary Order code STD10NM65N Marking 10NM65N Package DPAK Packing Tape and reel DS5566 - Rev 4 - May 2018 For further information contact your local STMicroelectronics sales office. www.st.com STD10NM65N Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 650 V VGS Gate-source voltage ±25 V Drain current (continuous) at TC = 25 °C 9 A Drain current (continuous) at TC = 100 °C 5.7 A Drain current (pulsed) 36 A Total dissipation at TC = 25 °C 90 W Peak diode recovery voltage slope 15 Drain-source voltage slope (VDD = 520 V, ID = 9 A, VGS = 10 V) 25 ID ID IDM (1) PTOT dv/dt (2) dv/dt Tj Operating junction temperature range Tstg V/ns -55 to 150 °C Value Unit Thermal resistance junction-case 1.39 °C/W Thermal resistance junction-pcb 50 °C/W Value Unit Storage temperature range 1. Pulse width limited by safe operating area. 2. ISD ≤ 9 A, di/dt ≤ 400 A/μs, VDSpeak ≤ V(BR)DSS, VDD = 80% V(BR)DSS. Table 2. Thermal data Symbol Rthj-case Rthj-pcb (1) Parameter 1. When mounted on 1inch² FR-4, 2 Oz copper board. Table 3. Avalanche characteristics Symbol DS5566 - Rev 4 Parameter IAS Avalanche current, repetitive or not-repetitive (pulse width limited by Tj Max) 2.5 A EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAS, VDD = 50 V) 200 mJ page 2/18 STD10NM65N Electrical characteristics 2 Electrical characteristics (TCASE = 25 °C unless otherwise specified) Table 4. On/off states Symbol Parameter V(BR)DSS Drain-source breakdown voltage Test conditions Min. ID = 1 mA, VGS = 0 V Typ. 650 Zero gate voltage drain current IGSS Gate body leakage current VDS = 0 V, VGS = ±20 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source on resistance VGS = 10 V, ID = 4.5 A VGS = 0 V, VDS = 650 V, TC = 125 °C 1 µA 100 µA ±100 nA 3 4 V 0.43 0.48 Ω Typ. Max. Unit - pF - pF - nC (1) 2 Unit V VGS = 0 V, VDS = 650 V IDSS Max. 1. Defined by design, not subject to production test. Table 5. Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Coss eq. (1) Equivalent output capacitance Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge Test conditions Min. 850 VDS = 50 V, f = 1 MHz, VGS = 0 V - 53 4 VDS = 0 to 520 V, VGS = 0 V VDD = 520 V, ID = 9 A, VGS = 0 to 10 V (see Figure 13. Test circuit for gate charge behavior) - 90 25 - 4 14 1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. Table 6. Switching times Symbol td(on) tr td(off) tf(i) DS5566 - Rev 4 Parameter Test conditions Turn-on delay time VDD = 325 V, ID = 4.5 A, Rise time RG = 4.7 Ω, VGS = 10 V Turn-off delay time (see Figure 12. Test circuit for resistive load switching times and Figure 17. Switching time waveform) Fall time Min. Typ. Max. Unit - ns 12 - 8 50 20 page 3/18 STD10NM65N Electrical characteristics Table 7. Source drain diode Symbol Parameter Test conditions ISD Source-drain current ISDM (1) Source-drain current (pulsed) VSD (2) Forward on voltage ISD = 9 A, VGS = 0 V trr Reverse recovery time ISD = 9 A, di/dt = 100 A/µs Qrr Reverse recovery charge IRRM Reverse recovery current VDD = 100 V (see Figure 14. Test circuit for inductive load switching and diode recovery times) trr Reverse recovery time ISD = 9 A, di/dt = 100 A/µs Qrr Reverse recovery charge IRRM Reverse recovery current VDD = 100 V (see Figure 14. Test circuit for inductive load switching and diode recovery times) Min. Typ. Max. Unit 9 - 36 - - - 1.3 A V 330 ns 3 μC 19 A 430 ns 4 μC 19 A 1. Pulse width limited by safe operating area. 2. Pulsed: pulse duration = 300 μs, duty cycle 1.5%. DS5566 - Rev 4 page 4/18 STD10NM65N Electrical characteristics curves 2.1 Electrical characteristics curves Figure 1. Safe operating area Figure 2. Thermal impedance HV41670 ID(A) Tj=150°C Tc=25°C 4 Single pulse 2 1 8 6 Op Li erati mi on ted in by thi M sA ax r Rd ea is s(o n) 10 4 2 10 0 8 6 100 100 m s 1ms 4 10ms 2 10 GC20460 K 10-1 -1 8 6 4 2 -2 10 10 -1 2 4 6 8 10 0 2 4 6 8 10 1 2 4 6 8 10 2 2 4 6 8 10 3 VDS(V) 10-2 10-5 Figure 3. Output characterisics ID(A) VGS=10V 10-2 tp (s) 10-1 HV41695 ID(A) VDS=20V 20 6V 15 10-3 Figure 4. Transfer characteristics HV41690 20 10-4 15 10 10 5V 5 5 4V 0 10 30 VDS(V) 20 Figure 5. Static drain-source on resistance HV41760 R DS(on) 0 8 6 4 2 VGS(V) Figure 6. Gate charge vs gate-source voltage HV41720 VGS (V) (Ω) 0.6 VDD=520V 12 I D =9A VGS =10V 0.5 9 0.4 6 0.3 0.2 DS5566 - Rev 4 3 0 2 4 6 8 I D(A) 0 5 10 15 20 25 Qg(nC) page 5/18 STD10NM65N Electrical characteristics curves Figure 8. Normalized gate threshold voltage vs temperature Figure 7. Capacitance variations HV41730 C (pF) HV41740 VGS(th) (norm) 4 ID =250µA 2 10 Ciss 3 1.1 8 6 4 1.0 2 10 2 8 6 0.9 Coss 4 2 10 0.8 1 8 6 Crss 4 0.7 2 10 0 10 -1 2 4 6 8 10 0 2 4 6 8 10 1 2 4 6 8 10 2 0.6 VDS (V) -100 Figure 9. Normalized on resistance vs temperature RDS(on) (norm) 2.5 0 50 100 150 TJ (°C) Figure 10. Source-drain diode forward characteristic HV41750 HV27230 VSD (V) VGS =10V ID=4.5A TJ =-50 °C 0.9 2.0 0.8 1.5 0.7 1.0 0.6 0.5 0.5 0 -100 -50 25 °C 150 °C -50 0 50 100 0.4 150 TJ ( °C) 0 2 4 6 8 10 I SD (A) Figure 11. Normalized V(BR)DSS vs temperature HV41700 V(BR)DSS VGS=0 ID=1mA (norm) 1.1 1.05 1.0 0.95 0.90 DS5566 - Rev 4 -50 0 50 100 TJ (°C) page 6/18 STD10NM65N Test circuits 3 Test circuits Figure 12. Test circuit for resistive load switching times Figure 13. Test circuit for gate charge behavior VDD 12 V 2200 + μF 3.3 μF VDD VD VGS 1 kΩ 100 nF RL IG= CONST VGS RG 47 kΩ + pulse width D.U.T. 2.7 kΩ 2200 μF pulse width D.U.T. 100 Ω VG 47 kΩ 1 kΩ AM01469v1 AM01468v1 Figure 14. Test circuit for inductive load switching and diode recovery times D G A D.U.T. S 25 Ω A L A B B 3.3 µF D G + VD 100 µH fast diode B Figure 15. Unclamped inductive load test circuit RG 1000 + µF 2200 + µF VDD 3.3 µF VDD ID D.U.T. S D.U.T. Vi _ pulse width AM01471v1 AM01470v1 Figure 16. Unclamped inductive waveform Figure 17. Switching time waveform V(BR)DSS ton VD td(on) 90% IDM tf 90% 10% 10% 0 ID VDD toff td(off) tr VDD VGS 0 VDS 90% 10% AM01472v1 AM01473v1 DS5566 - Rev 4 page 7/18 STD10NM65N Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DS5566 - Rev 4 page 8/18 STD10NM65N DPAK (TO-252) type A2 package information 4.1 DPAK (TO-252) type A2 package information Figure 18. DPAK (TO-252) type A2 package outline 0068772_type-A2_rev25 DS5566 - Rev 4 page 9/18 STD10NM65N DPAK (TO-252) type A2 package information Table 8. DPAK (TO-252) type A2 mechanical data Dim. mm Min. Max. A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 b 0.64 0.90 b4 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 D 6.00 6.20 D1 4.95 E 6.40 E1 5.10 5.20 5.30 e 2.159 2.286 2.413 e1 4.445 4.572 4.699 H 9.35 10.10 L 1.00 1.50 L1 2.60 2.80 3.00 L2 0.65 0.80 0.95 L4 0.60 R V2 DS5566 - Rev 4 Typ. 5.10 5.25 6.60 1.00 0.20 0° 8° page 10/18 STD10NM65N DPAK (TO-252) type C2 package information 4.2 DPAK (TO-252) type C2 package information Figure 19. DPAK (TO-252) type C2 package outline 0068772_C2_25 DS5566 - Rev 4 page 11/18 STD10NM65N DPAK (TO-252) type C2 package information Table 9. DPAK (TO-252) type C2 mechanical data Dim. mm Min. Typ. Max. A 2.20 2.30 2.38 A1 0.90 1.01 1.10 A2 0.00 0.10 b 0.72 0.85 b4 5.13 c 0.47 0.60 c2 0.47 0.60 D 6.00 D1 5.10 E 6.50 E1 5.20 e 2.186 2.286 2.386 H 9.80 10.10 10.40 L 1.40 1.50 1.70 L1 L2 6.20 5.60 6.60 6.70 5.50 0.90 1.25 0.51 BSC 0.60 L6 DS5566 - Rev 4 6.10 5.46 2.90 REF L3 L4 5.33 0.80 1.00 1.80 BSC θ1 5° 7° 9° θ2 5° 7° 9° V2 0° 8° page 12/18 STD10NM65N DPAK (TO-252) type C2 package information Figure 20. DPAK (TO-252) recommended footprint (dimensions are in mm) FP_0068772_25 DS5566 - Rev 4 page 13/18 STD10NM65N DPAK (TO-252) packing information 4.3 DPAK (TO-252) packing information Figure 21. DPAK (TO-252) tape outline 10 pitches cumulative tolerance on tape +/- 0.2 mm T P0 Top cover tape P2 D E F B1 K0 For machine ref. only including draft and radii concentric around B0 W B0 A0 P1 D1 User direction of feed R Bending radius User direction of feed AM08852v1 DS5566 - Rev 4 page 14/18 STD10NM65N DPAK (TO-252) packing information Figure 22. DPAK (TO-252) reel outline T 40mm min. access hole at slot location B D C N A G measured at hub Tape slot in core for tape start 2.5mm min.width Full radius AM06038v1 Table 10. DPAK (TO-252) tape and reel mechanical data Tape Dim. mm mm Dim. Min. Max. A0 6.8 7 A B0 10.4 10.6 B 1.5 12.1 C 12.8 1.6 D 20.2 G 16.4 50 B1 DS5566 - Rev 4 Reel Min. Max. 330 13.2 D 1.5 D1 1.5 E 1.65 1.85 N F 7.4 7.6 T K0 2.55 2.75 P0 3.9 4.1 Base qty. 2500 P1 7.9 8.1 Bulk qty. 2500 P2 1.9 2.1 R 40 T 0.25 0.35 W 15.7 16.3 18.4 22.4 page 15/18 STD10NM65N Revision history Table 11. Document revision history Date Version Changes 26-Oct-2007 1 Initial release. 07-Feb-2008 2 Document status promoted from preliminary data to datasheet. 14-Oct-2008 3 Table 4: Avalanche characteristics has been corrected. The part numbers STF10NM65N, STP10NM65N and STU10NM65N have been moved to a separate datasheet. 16-May-2018 4 Removed maturity status indication from cover page. The document status is production data. Updated features and description in cover page, Section 1 Electrical ratings, Section 2 Electrical characteristics, Section 2.1 Electrical characteristics curves and Section 4 Package information. Minor text changes. DS5566 - Rev 4 page 16/18 STD10NM65N Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.1 DPAK (TO-252) type A2 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2 DPAK (TO-252) type C2 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.3 DPAK (TO-252) packing information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 DS5566 - Rev 4 page 17/18 STD10NM65N IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2018 STMicroelectronics – All rights reserved DS5566 - Rev 4 page 18/18