STF12N60M2
N-channel 600 V, 0.395 Ω typ., 9 A MDmesh™ M2
Power MOSFET in a TO-220FP package
Datasheet - production data
Features
1
2
Order code
VDS
RDS(on) max.
ID
PTOT
STF12N60M2
600 V
0.450 Ω
9A
25 W
•
•
•
•
3
Extremely low gate charge
Excellent output capacitance (COSS) profile
100% avalanche tested
Zener-protected
Applications
TO-220FP
•
Figure 1: Internal schematic diagram
D(2)
Switching applications
Description
This device is an N-channel Power MOSFET
developed using MDmesh™ M2 technology.
Thanks to its strip layout and an improved vertical
structure, the device exhibits low on-resistance
and optimized switching characteristics,
rendering it suitable for the most demanding high
efficiency converters.
G(1)
S(3)
AM15572v1_no_tab
Table 1: Device summary
Order code
Marking
Package
Packing
STF12N60M2
12N60M2
TO-220FP
Tube
May 2015
DocID027908 Rev 1
This is information on a product in full production.
1/13
www.st.com
Contents
STF12N60M2
Contents
1
Electrical ratings ............................................................................. 3
2
Electrical characteristics ................................................................ 4
2.1
Electrical characteristics (curves) ...................................................... 6
3
Test circuits ..................................................................................... 8
4
Package information ....................................................................... 9
4.1
5
2/13
TO-220FP package information ...................................................... 10
Revision history ............................................................................ 12
DocID027908 Rev 1
STF12N60M2
1
Electrical ratings
Electrical ratings
Table 2: Absolute maximum ratings
Symbol
VGS
(1)
ID
(2)
IDM
PTOT
Parameter
Gate-source voltage
Value
Unit
±25
V
Drain current (continuous) at Tcase = 25 °C
9
Drain current (continuous) at Tcase = 100 °C
5.7
Drain current (pulsed)
36
A
W
Total dissipation at Tcase = 25 °C
25
dv/dt
(3)
Peak diode recovery voltage slope
15
dv/dt
(4)
MOSFET dv/dt ruggedness
50
VISO
Insulation withstand voltage (RMS) from all three leads
to external heat sink (t = 1 s; TC = 25 °C)
2.5
Tstg
Storage temperature
Tj
-55 to 150
Maximum junction temperature
150
A
V/ns
kV
°C
Notes:
(1)
(2)
Limited by maximum junction temperature.
Pulse width is limited by safe operating area.
(3)
ISD ≤ 9 A, di/dt=400 A/μs; VDS(peak) < V(BR)DSS, VDD = 80% V(BR)DSS.
(4)
VDS ≤ 480 V.
Table 3: Thermal data
Symbol
Parameter
Rthj-case
Thermal resistance junction-case
Rthj-amb
Thermal resistance junction-ambient
Value
5
62.5
Unit
°C/W
Table 4: Avalanche characteristics
Symbol
(1)
IAR
(2)
EAR
Parameter
Value
Unit
Avalanche current, repetitive or not repetitive
2.6
A
Single pulse avalanche energy
117
mJ
Notes:
(1)
(2)
Pulse width limited by Tjmax.
starting Tj = 25 °C, ID = IAR, VDD = 50 V.
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3/13
Electrical characteristics
2
STF12N60M2
Electrical characteristics
(Tcase = 25 °C unless otherwise specified)
Table 5: Static
Symbol
V(BR)DSS
Parameter
Test conditions
Drain-source breakdown
voltage
VGS = 0 V, ID = 1 mA
Min.
Typ.
Max.
600
Unit
V
VGS = 0 V, VDS = 600 V
1
VGS = 0 V, VDS = 600 V,
Tcase = 125 °C
100
±10
µA
3
4
V
0.395
0.450
Ω
Min.
Typ.
Max.
Unit
-
538
-
-
29
-
-
1.1
-
IDSS
Zero gate voltage drain
current
IGSS
Gate-body leakage current
VDS = 0 V, VGS = ±25 V
VGS(th)
Gate threshold voltage
VDS = VGS, ID = 250 µA
RDS(on)
Static drain-source onresistance
VGS = 10 V, ID = 4.5 A
2
µA
Table 6: Dynamic
Symbol
Parameter
Ciss
Input capacitance
Coss
Output capacitance
Crss
Reverse transfer
capacitance
Coss
Test conditions
VDS = 100 V, f = 1 MHz,
VGS = 0 V
pF
Equivalent output
capacitance
VDS = 0 to 480 V, VGS = 0 V
-
106
-
pF
RG
Intrinsic gate resistance
f = 1 MHz, ID = 0 A
-
7
-
Ω
Qg
Total gate charge
-
16
-
Qgs
Gate-source charge
-
2.3
-
Qgd
Gate-drain charge
VDD = 400 V, ID = 9 A,
VGS = 10 V (see Figure 15:
"Gate charge test circuit")
-
8.5
-
eq.
(1)
nC
Notes:
(1)
Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS
increases from 0 to 80% VDSS.
Table 7: Switching times
Symbo
l
td(on)
tr
td(off)
tf
4/13
Parameter
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Test conditions
Min.
Typ.
Max.
VDD = 300 V, ID = 4.5 A
RG = 4.7 Ω, VGS = 10 V (see
Figure 14: "Switching times
test circuit for resistive load"
and Figure 19: "Switching
time waveform")
-
9.2
-
DocID027908 Rev 1
-
9.2
-
-
56
-
-
18
-
Unit
ns
STF12N60M2
Electrical characteristics
Table 8: Source-drain diode
Symbol
ISD
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Source-drain current
-
9
A
(1)
Source-drain current
(pulsed)
-
36
A
(2)
Forward on voltage
VGS = 0 V, ISD = 9 A
-
1.6
V
trr
Reverse recovery time
-
284
ns
Qrr
Reverse recovery charge
-
2.4
µC
IRRM
Reverse recovery current
ISD = 9 A, di/dt = 100 A/µs,
VDD = 60 V (see Figure 16:
"Test circuit for inductive
load switching and diode
recovery times")
-
20.5
A
-
454
ns
-
4.8
µC
-
21
A
ISDM
VSD
trr
Reverse recovery time
Qrr
Reverse recovery charge
IRRM
Reverse recovery current
ISD = 9 A, di/dt = 100 A/µs,
VDD = 60 V, Tj = 150 °C (see
Figure 16: "Test circuit for
inductive load switching and
diode recovery times")
Notes:
(1)
(2)
Pulse width is limited by safe operating area.
Pulse test: pulse duration = 300 µs, duty cycle 1.5%.
DocID027908 Rev 1
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Electrical characteristics
2.1
6/13
STF12N60M2
Electrical characteristics (curves)
Figure 2: Safe operating area
Figure 3: Thermal impedance
Figure 4: Output characteristics
Figure 5: Transfer characteristics
Figure 6: Gate charge vs gate-source voltage
Figure 7: Static drain-source on-resistance
DocID027908 Rev 1
STF12N60M2
Electrical characteristics
Figure 8: Capacitance variations
Figure 9: Normalized gate threshold voltage
vs temperature
AM03184v1
VGS(th)
(norm)
1.10
1.00
ID = 250 µA
0.90
0.80
0.70
-50
50
0
100
Tj(°C)
Figure 10: Normalized on-resistance vs
temperature
Figure 11: Normalized V(BR)DSS vs
temperature
Figure 12: Output capacitance stored energy
Figure 13: Source- drain diode forward
characteristics
VSD
(V)
GIPG290120151002ALS
1.1
Tj = -50 °C
1.0
Tj = -25 °C
0.9
Tj = 150 °C
0.8
0.7
0.6
0.5
DocID027908 Rev 1
0
4
8
12
16
ISD (A)
7/13
Test circuits
3
STF12N60M2
Test circuits
Figure 14: Switching times test circuit for resistive
load
Figure 15: Gate charge test circuit
Figure 16: Test circuit for inductive load switching
and diode recovery times
Figure 17: Unclamped inductive load test circuit
Figure 18: Unclamped inductive waveform
Figure 19: Switching time waveform
8/13
DocID027908 Rev 1
STF12N60M2
4
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
DocID027908 Rev 1
9/13
Package information
4.1
STF12N60M2
TO-220FP package information
Figure 20: TO-220FP package outline
7012510_Rev_K_B
10/13
DocID027908 Rev 1
STF12N60M2
Package information
Table 9: TO-220FP package mechanical data
mm
Dim.
Min.
Typ.
Max.
A
4.4
4.6
B
2.5
2.7
D
2.5
2.75
E
0.45
0.7
F
0.75
1
F1
1.15
1.70
F2
1.15
1.70
G
4.95
5.2
G1
2.4
2.7
H
10
10.4
L2
16
L3
28.6
30.6
L4
9.8
10.6
L5
2.9
3.6
L6
15.9
16.4
L7
9
9.3
Dia
3
3.2
DocID027908 Rev 1
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Revision history
5
STF12N60M2
Revision history
Table 10: Document revision history
12/13
Date
Revision
22-May-2015
1
DocID027908 Rev 1
Changes
First release.
STF12N60M2
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