STF12N65M2

STF12N65M2 N-channel 650 V, 0.42 Ω typ., 8 A MDmesh™ M2 Power MOSFET in a TO-220FP package Datasheet - production data Features     Order code VDS RDS(on) max. ID STF12N65M2 650 V 0.50 Ω 8A Extremely low gate charge Excellent output capacitance (COSS) profile 100% avalanche tested Zener-protected Applications TO-220FP  Figure 1: Internal schematic diagram D(2) Switching applications Description This device is an N-channel Power MOSFET developed using MDmesh™ M2 technology. Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance and optimized switching characteristics, rendering it suitable for the most demanding high efficiency converters. G(1) S(3) AM15572v1_no_tab Table 1: Device summary Order code Marking Package Packing STF12N65M2 12N65M2 TO-220FP Tube June 2017 DocID027318 Rev 3 This is information on a product in full production. 1/13 www.st.com Contents STF12N65M2 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package information ....................................................................... 9 4.1 5 2/13 TO-220FP package information ...................................................... 10 Revision history ............................................................................ 12 DocID027318 Rev 3 STF12N65M2 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol VGS Parameter Gate-source voltage Value Unit ±25 V Drain current (continuous) at Tcase = 25 °C 8 Drain current (continuous) at Tcase = 100 °C 5 IDM(2) Drain current (pulsed) 32 A PTOT W ID(1) A Total dissipation at Tcase = 25 °C 25 dv/dt(3) Peak diode recovery voltage slope 15 dv/dt(4) MOSFET dv/dt ruggedness 50 VISO Insulation withstand voltage (RMS) from all three leads to external heat sink (t = 1 s; TC = 25 °C) 2.5 kV Tstg Storage temperature range -55 to 150 °C Value Unit Tj Operating junction temperature range V/ns Notes: (1) Limited by package. (2) Pulse width is limited by safe operating area. (3) ISD ≤ 8 A, di/dt = 400 A/μs; VDS(peak) < V(BR)DSS, VDD = 400 V (4) VDS ≤ 520 V Table 3: Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case Rthj-amb Thermal resistance junction-ambient 5 62.5 °C/W Table 4: Avalanche characteristics Symbol Parameter Value Unit IAR Avalanche current, repetitive or not repetitive (pulse width limited by Tjmax.) 1.6 A Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR; VDD = 50 V) 250 mJ EAS(1) Notes: (1) Starting Tj = 25 °C, ID = IAR, VDD = 50 V. DocID027318 Rev 3 3/13 Electrical characteristics 2 STF12N65M2 Electrical characteristics (Tcase = 25 °C unless otherwise specified) Table 5: Static Symbol Parameter Test conditions V(BR)DSS Drain-source breakdown voltage IDSS Zero-gate voltage drain current IGSS VGS = 0 V, ID = 1 mA Min. Typ. Max. 650 Unit V VGS = 0 V, VDS = 650 V 1 VGS = 0 V, VDS = 600 V, Tcase = 125 °C(1) 100 Gate-body leakage current VDS = 0 V, VGS = ±25 V ±10 µA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 3 4 V RDS(on) Static drain-source onresistance VGS = 10 V, ID = 4 A 0.42 0.50 Ω Min. Typ. Max. Unit - 535 - - 25 - - 1.1 - 2 µA Notes: (1)Defined by design, not subject to production test. Table 6: Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Coss Test conditions VDS = 100 V, f = 1 MHz, VGS = 0 V pF Equivalent output capacitance VDS = 0 to 520 V, VGS = 0 V - 144 - pF RG Intrinsic gate resistance f = 1 MHz, ID = 0 A - 7 - Ω Qg Total gate charge - 16.7 - Qgs Gate-source charge - 2.6 - Qgd Gate-drain charge VDD = 520 V, ID = 8 A, VGS = 0 to10 V (see Figure 15: "Test circuit for gate charge behavior") - 8.6 - eq. (1) nC Notes: (1) Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. Table 7: Switching times Symbol td(on) tr td(off) tf 4/13 Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions Min. Typ. Max. VDD = 325 V, ID = 4 A RG = 4.7 Ω, VGS = 10 V (see Figure 14: "Test circuit for resistive load switching times" and Figure 19: "Switching time waveform") - 9 - - 7 - - 34 - - 13.5 - DocID027318 Rev 3 Unit ns STF12N65M2 Electrical characteristics Table 8: Source-drain diode Symbol Parameter Test conditions ISD(1) Source-drain current ISDM(2) Source-drain current (pulsed) VSD(3) Forward on voltage trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current Min. Typ. Max. Unit - 8 A - 32 A VGS = 0 V, ISD = 8 A - 1.6 V ISD = 8 A, di/dt = 100 A/µs, VDD = 60 V (see Figure 16: "Test circuit for inductive load switching and diode recovery times") - 313 ns - 2.7 µC - 17 A ISD = 8 A, di/dt = 100 A/µs, VDD = 60 V, Tj = 150 °C (see Figure 16: "Test circuit for inductive load switching and diode recovery times") - 462 ns - 4.1 µC - 17.5 A Notes: (1)Limited by package. (2) Pulse width is limited by safe operating area. (3) Pulse test: pulse duration = 300 µs, duty cycle 1.5%. DocID027318 Rev 3 5/13 Electrical characteristics 2.1 STF12N65M2 Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance GIPD161220141813MT R DS(on) (Ω) V GS= 10V 0.44 0.43 0.42 0.41 0.40 0 6/13 DocID027318 Rev 3 2 4 6 8 ID(A) STF12N65M2 Electrical characteristics Figure 9: Normalized gate threshold voltage vs temperature Figure 8: Capacitance variations GIPD161220141823MT C (pF) Ciss 1000 GIPD180920141442FSR V GS(th) (norm) ID = 250 µ A 1.1 1.0 100 Coss 0.9 10 0.8 Crss 1 0.7 0.1 0.1 1 10 100 V DS(V) Figure 10: Normalized on-resistance vs temperature 0.6 -75 -25 75 25 125 T j(°C) Figure 11: Normalized V(BR)DSS vs temperature GIPD180920141448FSR V (BR)DSS (norm) 1.08 ID= 1m A 1.04 1.00 0.96 0.92 0.88 -75 Figure 12: Output capacitance stored energy GIPD171220141020MT E (µJ) -25 25 125 75 Figure 13: Source- drain diode forward characteristics GIPD161220141847MT V SD (V) 1.1 4 T j(°C) T j= -50°C 1 3 0.9 2 T j= 25°C 0.8 T j= 150°C 0.7 1 0.6 0 0 100 200 300 400 500 600 V DS(V) 0.5 DocID027318 Rev 3 0 2 4 6 8 ISD(A) 7/13 Test circuits 3 STF12N65M2 Test circuits Figure 15: Test circuit for gate charge behavior Figure 14: Test circuit for resistive load switching times Figure 16: Test circuit for inductive load switching and diode recovery times Figure 17: Unclamped inductive load test circuit Figure 18: Unclamped inductive waveform 8/13 DocID027318 Rev 3 Figure 19: Switching time waveform STF12N65M2 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DocID027318 Rev 3 9/13 Package information 4.1 STF12N65M2 TO-220FP package information Figure 20: TO-220FP package outline 7012510_Rev_12_B 10/13 DocID027318 Rev 3 STF12N65M2 Package information Table 9: TO-220FP package mechanical data mm Dim. Min. Typ. Max. A 4.4 4.6 B 2.5 2.7 D 2.5 2.75 E 0.45 0.7 F 0.75 1 F1 1.15 1.70 F2 1.15 1.70 G 4.95 5.2 G1 2.4 2.7 H 10 10.4 L2 16 L3 28.6 30.6 L4 9.8 10.6 L5 2.9 3.6 L6 15.9 16.4 L7 9 9.3 Dia 3 3.2 DocID027318 Rev 3 11/13 Revision history 5 STF12N65M2 Revision history Table 10: Document revision history 12/13 Date Revision Changes 16-Dec-2014 1 First release. 11-Mar-2015 2 Updated features in cover page. Minor text changes 06-Jun-2017 3 Updated Section 1: "Electrical ratings", Section 2: "Electrical characteristics" and Section 2.1: "Electrical characteristics (curves)". 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All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2017 STMicroelectronics – All rights reserved DocID027318 Rev 3 13/13