STF18N60DM2

STF18N60DM2 Datasheet N-channel 600 V, 0.260 Ω typ., 12 A MDmesh DM2 Power MOSFET in a TO-220FP package Features 2 1 3 TO-220FP D(2) • • • • • • Order code VDS RDS(on) max. ID STF18N60DM2 600 V 0.295 Ω 12 A Fast-recovery body diode Extremely low gate charge and input capacitance Low on-resistance 100% avalanche tested Extremely high dv/dt ruggedness Zener-protected Applications G(1) • Switching applications Description S(3) AM15572v1_no_tab This high-voltage N-channel Power MOSFET is part of the MDmesh DM2 fastrecovery diode series. It offers very low recovery charge (Qrr) and time (trr) combined with low RDS(on), rendering it suitable for the most demanding high-efficiency converters and ideal for bridge topologies and ZVS phase-shift converters. Product status links STF18N60DM2 Product summary Order code STF18N60DM2 Marking 18N60DM2 Package TO-220FP Packing Tube DS10966 - Rev 5 - June 2019 For further information contact your local STMicroelectronics sales office. www.st.com STF18N60DM2 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Value Unit Gate-source voltage ±25 V ID Drain current (continuous) at Tcase = 25 °C 12 A ID Drain current (continuous) at Tcase= 100 °C 7.6 A Drain current (pulsed) 48 A Total power dissipation at Tcase = 25 °C 25 W dv/dt(2) Peak diode recovery voltage slope 40 dv/dt(3) MOSFET dv/dt ruggedness 50 Insulation withstand voltage (RMS) from all three leads to external heat sink 2.5 VGS IDM (1) PTOT VISO Parameter V/ns kV (t = 1 s; TC = 25 °C) Tstg Tj Storage temperature range Operating junction temperature range –55 to 150 °C °C 1. Pulse width is limited by safe operating area. 2. ISD ≤ 12, di/dt ≤ 400 A/µs, VDS(peak) < V(BR)DSS, VDD = 400 V 3. VDS ≤ 480 V Table 2. Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case Rthj-amb Thermal resistance junction-ambient Value 5 62.5 Unit °C/W Table 3. Avalanche characteristics Symbol IAR EAR DS10966 - Rev 5 Parameter Avalanche current, repetitive or not repetitive (pulse width limited by Tjmax) Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) Value Unit 2.5 A 380 mJ page 2/12 STF18N60DM2 Electrical characteristics 2 Electrical characteristics (Tcase= 25 °C unless otherwise specified) Table 4. Static Symbol V(BR)DSS Parameter Drain-source breakdown voltage Test conditions VGS = 0 V, ID = 1 mA Min. Typ. 600 Zero gate voltage drain current 1 µA 100 µA ±5 µA 4 5 V 0.260 0.295 Ω Min. Typ. Max. Unit - 800 - pF - 40 - pF - 1.33 - pF VGS = 0 V, VDS = 600 V, Tcase = 125 °C (1) IGSS Gate-body leakage current VDS = 0 V, VGS = ±25 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source onresistance VGS = 10 V, ID = 6 A Unit V VGS = 0 V, VDS = 600 V IDSS Max. 3 1. Defined by design, not subject to production test. Table 5. Dynamic Symbol Parameter Test conditions Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Coss eq. (1) Equivalent output capacitance VDS = 0 to 480 V, f = 1 MHz, VGS = 0 V - 80 - pF RG Intrinsic gate resistance f = 1 MHz, ID=0 A - 5.6 - Ω Qg Total gate charge - 20 - nC Qgs Gate-source charge - 5.2 - nC Qgd Gate-drain charge - 8.5 - nC VDS = 100 V, f = 1 MHz, VGS = 0 V VDD = 480 V, ID = 12 A, VGS = 0 to 10 V (see Figure 14. Test circuit for gate charge behavior) 1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS Table 6. Switching times Symbol td(on) tr td(off) tf DS10966 - Rev 5 Parameter Test conditions Turn-on delay time Rise time Turn-off delay time Fall time VDD = 300 V, ID = 6 A RG = 4.7 Ω, VGS = 10 V (see Figure 13. Test circuit for resistive load switching times and Figure 18. Switching time waveform) Min. Typ. Max. Unit - 13.5 - ns - 8 - ns - 9.5 - ns - 32.5 - ns page 3/12 STF18N60DM2 Electrical characteristics Table 7. Source-drain diode Symbol ISD Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 12 A ISDM (1) Source-drain current (pulsed) - 48 A VSD (2) Forward on voltage - 1.6 V trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current VGS = 0 V, ISD = 12 A ISD = 12 A, di/dt = 100 A/µs, VDD = 60 V (see Figure 15. Test circuit for inductive load switching and diode recovery times) ISD = 12 A, di/dt = 100 A/µs, VDD = 60 V, Tj = 150 °C (see Figure 15. Test circuit for inductive load switching and diode recovery times) - 125 ns - 0.675 μC - 11 A - 190 ns - 1.225 μC - 13 A 1. Pulse width is limited by safe operating area. 2. Pulse test: pulse duration = 300 µs, duty cycle 1.5%. DS10966 - Rev 5 page 4/12 STF18N60DM2 Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Figure 2. Thermal impedance Figure 1. Safe operating area GC20940 on ) 10 -1 10 μs S( O lim per ite ati d on by in m th ax is . R ar ea D is 10 1 10 0 K GIPG260320151622ALS ID (A) 10 -1 100 μs 1 ms 10 ms 10 -2 T j ≤ 150 °C T c = 25 °C single pulse 10 -2 10 -1 10 0 V DS (V) 10 2 10 1 Figure 3. Output characteristics ID (A) 10 -3 10 -4 10 -1 ID (A) GIPG290415FQ6GOCH V GS = 7,8,9,10 V 24 20 20 16 10 0 t p (s) GIPG290415FQ6GTCH V DS = 12 V 16 V GS = 6 V 12 12 8 8 4 4 V GS = 5 V 2 4 6 8 10 12 V DS (V) Figure 5. Gate charge vs gate-source voltage VGS (V) V DD = 480 V I D = 12 A V DS 0 2 R DS(on) (Ω) 600 0.275 500 8 400 6 300 4 200 2 100 3 4 5 6 7 8 V GS (V) Figure 6. Static drain-source on-resistance (V) GIPG250320151541ALSVDS 12 10 10 -2 Figure 4. Transfer characteristics 24 0 0 10 -3 GIPG250320151528ALS V GS = 10 V 0.270 0.265 0.260 0 0 DS10966 - Rev 5 4 8 12 16 20 0 Q g (nC) 0.255 0.250 0 2 4 6 8 10 12 I D (A) page 5/12 STF18N60DM2 Electrical characteristics (curves) Figure 7. Capacitance variations C (pF) GIPG250320151620ALS Figure 8. Normalized gate threshold voltage vs temperature V GS(th) (norm.) GIPG250320151515ALS 1.1 10 3 I D = 250 μA C ISS 1.0 10 2 0.9 C OSS f = 1 MHz 10 1 0.8 0.7 C RSS 10 0 10 -1 10 0 10 1 V DS (V) 10 2 Figure 9. Normalized on-resistance vs temperature R DS(on) (norm.) GIPG250320151534ALS 2.2 0.6 -75 V (BR)DSS (norm.) 1.8 1.04 1.4 1.00 1.0 0.96 0.6 0.92 -25 25 75 125 T j (°C) Figure 11. Source-drain diode forward characteristics V SD (V) GIPG250320151630ALS T j = -50 °C 1.1 125 T j (°C) GIPG250320151522ALS 0.88 -75 I D = 1 mA -25 25 75 125 T j (°C) Figure 12. Output capacitance stored energy E OSS (µJ) GIPD280120161127EOS 5 0.9 T j = 25 °C 4 0.8 3 T j = 150 °C 0.7 2 0.6 1 DS10966 - Rev 5 75 6 1.0 0.5 0 25 Figure 10. Normalized V(BR)DSS vs temperature 1.08 V GS = 10 V 0.2 -75 -25 2 4 6 8 10 12 I SD (A) 0 0 100 200 300 400 500 600 V DS (V) page 6/12 STF18N60DM2 Test circuits 3 Test circuits Figure 13. Test circuit for resistive load switching times Figure 14. Test circuit for gate charge behavior VDD 12 V 2200 + μF 3.3 μF VDD VD VGS 1 kΩ 100 nF RL IG= CONST VGS RG 47 kΩ + pulse width D.U.T. 2.7 kΩ 2200 μF pulse width D.U.T. 100 Ω VG 47 kΩ 1 kΩ AM01469v1 AM01468v1 Figure 15. Test circuit for inductive load switching and diode recovery times D G A D.U.T. S 25 Ω A L A B B 3.3 µF D G + VD 100 µH fast diode B Figure 16. Unclamped inductive load test circuit RG 1000 + µF 2200 + µF VDD 3.3 µF VDD ID D.U.T. S D.U.T. Vi _ pulse width AM01471v1 AM01470v1 Figure 18. Switching time waveform Figure 17. Unclamped inductive waveform ton V(BR)DSS td(on) VD toff td(off) tr tf 90% 90% IDM VDD 10% 0 ID VDD AM01472v1 VGS 0 VDS 10% 90% 10% AM01473v1 DS10966 - Rev 5 page 7/12 STF18N60DM2 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 4.1 TO-220FP package information Figure 19. TO-220FP package outline 7012510_Rev_13_B DS10966 - Rev 5 page 8/12 STF18N60DM2 TO-220FP package information Table 8. TO-220FP package mechanical data Dim. mm Min. Max. A 4.40 4.60 B 2.50 2.70 D 2.50 2.75 E 0.45 0.70 F 0.75 1.00 F1 1.15 1.70 F2 1.15 1.70 G 4.95 5.20 G1 2.40 2.70 H 10.00 10.40 L2 DS10966 - Rev 5 Typ. 16.00 L3 28.60 30.60 L4 9.80 10.60 L5 2.90 3.60 L6 15.90 16.40 L7 9.00 9.30 Dia 3.00 3.20 page 9/12 STF18N60DM2 Revision history Table 9. Document revision history Date Revision 01-Apr-2015 1 Changes First release. Text edits throughout document 21-May-2015 2 In Section 2.1 Electrical characteristics (curves): - updated Figure 4: Output characteristics - updated Figure 5: Transfer characteristics 02-Jul-2015 3 Updated title and ID values in features and Table 1 28-Jan-2016 4 Updated Section 2.1: "Electrical characteristics (curves)". 10-Jun-2019 5 Modified Table 1. Absolute maximum ratings, Table 2. Thermal data, Table 4. Static and Table 7. Source-drain diode. Minor text changes. DS10966 - Rev 5 page 10/12 STF18N60DM2 Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4.1 TO-220FP package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 DS10966 - Rev 5 page 11/12 STF18N60DM2 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. 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Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2019 STMicroelectronics – All rights reserved DS10966 - Rev 5 page 12/12