STF18N65M2

STF18N65M2 N-channel 650 V, 0.275 Ω typ., 12 A MDmesh ™ M2 Power MOSFET in a TO-220FP package Datasheet − production data Features Order code VDS RDS(on) max ID STF18N65M2 650 V 0.33 Ω 12 A • Extremely low gate charge 3 1 • Excellent output capacitance (Coss) profile 2 • 100% avalanche tested TO-220FP • Zener-protected Applications Figure 1. Internal schematic diagram • Switching applications • LLC converters, resonant converters Description This device is an N-channel Power MOSFET developed using MDmesh™ M2 technology. Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance and optimized switching characteristics, rendering it suitable for the most demanding high efficiency converters. AM15572v1 Table 1. Device summary Order code Marking Package Packaging STF18N65M2 18N65M2 TO-220FP Tube January 2015 This is information on a product in full production. DocID026877 Rev 2 1/13 www.st.com 13 Contents STF18N65M2 Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Test circuits 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2/13 .............................................. 8 DocID026877 Rev 2 STF18N65M2 1 Electrical ratings Electrical ratings Table 2. Absolute maximum ratings Symbol VGS ID Parameter Value Unit ± 25 V (1) A Gate-source voltage Drain current (continuous) at TC = 25 °C ID 12 (1) Drain current (continuous) at TC = 100 °C 8 IDM(2) Drain current (pulsed) 48(1) A PTOT Total dissipation at TC = 25 °C 25 W Peak diode recovery voltage slope 15 V/ns MOSFET dv/dt ruggedness 50 V/ns 2500 V - 55 to 150 °C Value Unit 5 °C/W 62.5 °C/W Value Unit dv/dt (3) dv/dt(4) VISO Insulation withstand voltage (RMS) from all three leads to external heat sink (t = 1 s,TC = 25 °C) Tstg Storage temperature Tj A Operating junction temperature 1. Limited by maximum junction temperature 2. Pulse width limited by safe operating area 3. ISD ≤ 12 A, di/dt ≤ 400 A/µs; VDS peak < V(BR)DSS, VDD=400 V. 4. VDS ≤ 520V Table 3. Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case max Rthj-amb Thermal resistance junction-ambient max Table 4. Avalanche characteristics Symbol Parameter IAR Avalanche current, repetitive or not repetitive (pulse width limited by Tjmax ) 2 A EAS Single pulse avalanche energy (starting Tj=25°C, ID= IAR; VDD=50V) 450 mJ DocID026877 Rev 2 3/13 Electrical characteristics 2 STF18N65M2 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 5. On /off states Symbol V(BR)DSS Parameter Drain-source breakdown voltage Test conditions ID = 1 mA, VGS = 0 IDSS VDS = 650 V Zero gate voltage drain current (VGS = 0) VDS = 650 V, TC=125 °C IGSS Gate-body leakage current (VDS = 0) Min. Typ. Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source on-resistance Unit 650 V 1 µA 100 µA ±10 µA 3 4 V 0.275 0.33 Ω Min. Typ. Max. Unit - 770 - pF - 35 - pF - 1.2 - pF VGS = ± 25 V VGS(th) Max. 2 VGS = 10 V, ID = 6 A Table 6. Dynamic Symbol Ciss Parameter Test conditions Input capacitance VDS = 100 V, f = 1 MHz, VGS = 0 Coss Output capacitance Crss Reverse transfer capacitance Coss eq.(1) Equivalent output capacitance VDS = 0 to 520 V, VGS = 0 - 175 - pF RG Intrinsic gate resistance f = 1 MHz, ID = 0 - 6.1 - Ω Qg Total gate charge - 20 - nC Qgs Gate-source charge - 3.6 - nC Qgd Gate-drain charge VDD = 520 V, ID = 12 A, VGS = 10 V (see Figure 15) - 8.5 - nC 1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS Table 7. Switching times Symbol td(on) tr td(off) tf 4/13 Parameter Test conditions Turn-on delay time Rise time Turn-off delay time VDD = 325 V, ID = 6 A, RG = 4.7 Ω, VGS = 10 V (see Figure 14 and Figure 19) Fall time DocID026877 Rev 2 Min. Typ. Max. Unit - 11 - ns - 7.5 - ns - 46 - ns - 12.5 - ns STF18N65M2 Electrical characteristics Table 8. Source drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 12 A ISDM (1) Source-drain current (pulsed) - 48 A VSD (2) Forward on voltage - 1.6 V ISD trr ISD = 12 A, VGS = 0 Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ISD = 12 A, di/dt = 100 A/µs VDD = 60 V (see Figure 16) ISD = 12 A, di/dt = 100 A/µs VDD = 60 V, Tj = 150 °C (see Figure 16) - 331 ns - 3.4 µC - 20.5 A - 462 ns - 4.6 µC - 20 A 1. Pulse width limited by safe operating area. 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5% DocID026877 Rev 2 5/13 Electrical characteristics 2.1 STF18N65M2 Electrical characteristics (curves) Figure 2. Safe operating area ,'$ Figure 3. Thermal impedance  *,3*)65 Q 2 /LP SHUD LWH WLRQ G LQ E\ W P KLV D[ D 5 UHD LV '6  R —V     —V 7M ƒ& 7F ƒ& 6LQJOHSXOVH  PV PV 9'69  Figure 4. Output characteristics ,'$ Figure 5. Transfer characteristics *,3*$/6 9*6 9 ,' $   9*6 9       9*6 9   *,3*$/6 9'6 Y        9'69 Figure 6. Gate charge vs gate-source voltage *,3*$/6 9'6 9 9*6 9   9'6 9 ,' $      5'6RQ ȍ *,3*$/6   9*6 9          6/13       4JQ& 9*69 Figure 7. Static drain-source on-resistance        DocID026877 Rev 2        ,'$ STF18N65M2 Electrical characteristics Figure 8. Capacitance variations & S) Figure 9. Output capacitance stored energy (266 —- *,3*$/6 *,3*$/6   &LVV     &RVV        &UVV 9'69  Figure 10. Normalized gate threshold voltage vs temperature 9*6WK QRUP *,3*$/6 ,' —$    5'6RQ QRUP          7-ƒ& Figure 12. Source-drain diode forward characteristics 96' 9    9'69 *,3*$/6      Figure 11. Normalized on-resistance vs temperature     *,3*$/6   9*6 9     7-ƒ& Figure 13. Normalized V(BR)DSS vs temperature 9%5'66 QRUP *,3*$/6   7- ƒ&  ,' P$  7- ƒ&  7- ƒ&             ,6'$   DocID026877 Rev 2     7-ƒ& 7/13 Test circuits 3 STF18N65M2 Test circuits Figure 14. Switching times test circuit for resistive load Figure 15. Gate charge test circuit VDD 12V 47kΩ 1kΩ 100nF 3.3 μF 2200 RL μF IG=CONST VDD VGS 100Ω Vi=20V=VGMAX VD RG 2200 μF D.U.T. D.U.T. VG 2.7kΩ PW 47kΩ 1kΩ PW AM01468v1 Figure 16. Test circuit for inductive load switching and diode recovery times A A AM01469v1 Figure 17. Unclamped inductive load test circuit L A D G D.U.T. FAST DIODE B B VD L=100μH S 3.3 μF B 25 Ω 1000 μF D VDD 2200 μF 3.3 μF VDD ID G RG S Vi D.U.T. Pw AM01470v1 AM01471v1 Figure 18. Unclamped inductive waveform Figure 19. Switching time waveform ton V(BR)DSS tdon VD toff tr tdoff tf 90% 90% IDM 10% ID VDD 10% 0 VDD VDS 90% VGS AM01472v1 8/13 0 DocID026877 Rev 2 10% AM01473v1 STF18N65M2 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DocID026877 Rev 2 9/13 Package mechanical data STF18N65M2 Figure 20. TO-220FP drawing 7012510_Rev_K_B 10/13 DocID026877 Rev 2 STF18N65M2 Package mechanical data Table 9. TO-220FP mechanical data mm Dim. Min. Typ. Max. A 4.4 4.6 B 2.5 2.7 D 2.5 2.75 E 0.45 0.7 F 0.75 1 F1 1.15 1.70 F2 1.15 1.70 G 4.95 5.2 G1 2.4 2.7 H 10 10.4 L2 16 L3 28.6 30.6 L4 9.8 10.6 L5 2.9 3.6 L6 15.9 16.4 L7 9 9.3 Dia 3 3.2 DocID026877 Rev 2 11/13 Revision history 5 STF18N65M2 Revision history Table 10. Document revision history 12/13 Date Revision Changes 15-Dec-2014 1 First release. 12-Jan-2015 2 Added Chapter 2.1: Electrical characteristics (curves). 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All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved DocID026877 Rev 2 13/13