STF24N60DM2

STF24N60DM2 N-channel 600 V, 0.175 Ω typ., 18 A MDmesh™ DM2 Power MOSFET in a TO-220FP package Datasheet - production data Features Order code VDS @ TJmax RDS(on) max. ID STF24N60DM2 650 V 0.200 Ω 18 A       TO-220FP Figure 1: Internal schematic diagram Fast-recovery body diode Extremely low gate charge and input capacitance Low on-resistance 100% avalanche tested Extremely high dv/dt ruggedness Zener-protected Applications  Switching applications Description This high voltage N-channel Power MOSFET is part of the MDmesh™ DM2 fast recovery diode series. It offers very low recovery charge (Qrr) and time (trr) combined with low RDS(on), rendering it suitable for the most demanding high efficiency converters and ideal for bridge topologies and ZVS phase-shift converters. Table 1: Device summary Order code Marking Package Packing STF24N60DM2 24N60DM2 TO-220FP Tube September 2016 DocID025498 Rev 5 This is information on a product in full production. 1/13 www.st.com Contents STF24N60DM2 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package information ....................................................................... 9 4.1 5 2/13 TO-220FP package information ...................................................... 10 Revision history ............................................................................ 12 DocID025498 Rev 5 STF24N60DM2 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol VGS ID(1) IDM(2)(1) PTOT Parameter Gate-source voltage Value Unit ± 25 V Drain current (continuous) at TC = 25 °C 18 Drain current (continuous) at TC= 100 °C 11 Drain current (pulsed) 72 A W Total dissipation at TC = 25 °C 30 dv/dt(3) Peak diode recovery voltage slope 40 dv/dt(4) MOSFET dv/dt ruggedness 50 VISO Insulation withstand voltage (RMS) from all three leads to external heat sink (t = 1 s; TC = 25 °C) Tstg Storage temperature range Tj Max. operating junction temperature range A V/ns 2500 V –55 to 150 °C Notes: (1) Limited by package. (2) Pulse width is limited by safe operating area. (3) ISD ≤ 18 A, di/dt ≤ 400 A/µS, VDS(peak) < V(BR)DSS, VDD = 400 V. (4) VDS ≤ 480 V. Table 3: Thermal data Symbol Parameter Value Rthj-case Thermal resistance junction-case max. 4.2 Rthj-amb Thermal resistance junction-ambient max. 62.5 Unit °C/W Table 4: Avalanche characteristics Symbol Parameter Value Unit IAR Avalanche current, repetitive or not repetitive (pulse width limited by TJmax) 3.5 A EAS Single pulse avalanche energy (starting TJ =25 °C, ID = IAR; VDD = 50 V) 180 mJ DocID025498 Rev 5 3/13 Electrical characteristics 2 STF24N60DM2 Electrical characteristics (Tcase= 25 °C unless otherwise specified) Table 5: On /off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage VGS = 0 V, ID = 1 mA Min. Typ. Max. 600 Unit V VGS = 0 V, VDS = 600 V 1.5 µA VGS = 0 V, VDS = 600 V, TC = 125 °C (1) 100 µA Gate-body leakage current VDS = 0 V, VGS = ±25 V ±10 µA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 4 5 V RDS(on) Static drain-source onresistance VGS = 10 V, ID = 9 A 0.175 0.200 Ω Min. Typ. Max. Unit - 1055 - pF - 56 - pF - 2.4 - pF IDSS Zero gate voltage drain current IGSS 3 Notes: (1)Defined by design, not subject to production test. Table 6: Dynamic Symbol Parameter Test conditions Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Coss eq.(1) Equivalent output capacitance VDS = 0 to 480 V, VGS = 0 V - 259 - pF RG Intrinsic gate resistance f = 1 MHz, ID = 0 A - 7 - Ω Qg Total gate charge - 29 - nC Qgs Gate-source charge - 6 - nC Qgd Gate-drain charge VDD = 480 V, ID = 18 A, VGS = 10 V (see Figure 15: "Test circuit for gate charge behavior") - 12 - nC VDS = 100 V, f = 1 MHz, VGS = 0 V Notes: (1)C oss eq. is defined as a constant equivalent capacitance giving the same charging time as C OSS when VDS increases from 0 to 80% VDSS. 4/13 DocID025498 Rev 5 STF24N60DM2 Electrical characteristics Table 7: Switching times Symbol td(on) tr td(off) tf Parameter Test conditions Turn-on delay time VDD = 300 V, ID = 9 A RG = 4.7 Ω, VGS = 10 V (see Figure 14: "Test circuit for resistive load switching times" and Figure 19: "Switching time waveform") Rise time Turn-off-delay time Fall time Min. Typ. Max. Unit - 15 - ns - 8.7 - ns - 60 - ns - 15 - ns Min. Typ. Max. Unit Table 8: Source-drain diode Symbol Parameter Test conditions ISD Source-drain current - 18 A ISDM(1) Source-drain current (pulsed) - 72 A VSD (2) Forward on voltage VGS = 0 V, ISD = 18 A - 1.6 V trr Reverse recovery time - 155 ns Qrr Reverse recovery charge - 956 nC IRRM Reverse recovery current ISD = 18 A, di/dt = 100 A/µs, VDD = 60 V (see Figure 16: "Test circuit for inductive load switching and diode recovery times") - 12.5 A ISD = 18 A, di/dt = 100 A/µs, VDD = 60 V, Tj = 150 °C (see Figure 16: "Test circuit for inductive load switching and diode recovery times") - 200 ns - 1450 nC - 13 trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current A Notes: (1) Pulse width is limited by safe operating area. (2) Pulse test: pulse duration = 300 µs, duty cycle 1.5%. DocID025498 Rev 5 5/13 Electrical characteristics 2.1 STF24N60DM2 Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance 6/13 DocID025498 Rev 5 STF24N60DM2 Electrical characteristics Figure 8: Capacitance variations Figure 9: Output capacitance stored energy Figure 10: Normalized gate threshold voltage vs temperature Figure 11: Normalized on-resistance vs temperature Figure 12: Source-drain diode forward characteristics Figure 13: Normalized V(BR)DSS vs temperature DocID025498 Rev 5 7/13 Test circuits 3 8/13 STF24N60DM2 Test circuits Figure 14: Test circuit for resistive load switching times Figure 15: Test circuit for gate charge behavior Figure 16: Test circuit for inductive load switching and diode recovery times Figure 17: Unclamped inductive load test circuit Figure 18: Unclamped inductive waveform Figure 19: Switching time waveform DocID025498 Rev 5 STF24N60DM2 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DocID025498 Rev 5 9/13 Package information 4.1 STF24N60DM2 TO-220FP package information Figure 20: TO-220FP package outline 10/13 DocID025498 Rev 5 STF24N60DM2 Package information Table 9: TO-220FP package mechanical data mm Dim. Min. Typ. Max. A 4.4 4.6 B 2.5 2.7 D 2.5 2.75 E 0.45 0.7 F 0.75 1 F1 1.15 1.70 F2 1.15 1.70 G 4.95 5.2 G1 2.4 2.7 H 10 10.4 L2 16 L3 28.6 30.6 L4 9.8 10.6 L5 2.9 3.6 L6 15.9 16.4 L7 9 9.3 Dia 3 3.2 DocID025498 Rev 5 11/13 Revision history 5 STF24N60DM2 Revision history Table 10: Document revision history Date Revision 12-Nov-2013 1 First release. 2 – Modified: dv/dt value in Table 2 – Modified: IAR value in Table 4 – Modified: IDSS and VGS(th) in Table 5 – Minor text changes 03-Mar-2014 3 – Modified: Figure 1 – Modified: PTOT value and note 1 in Table 2 – Modified: Rthj-case value in Table 3 – Modified: IAR value in Table 4 – Minor text changes 05-Mar-2015 4 – Document status promoted from preliminary to production data. – Updated title, features and description in cover page. 20-Sep-2016 5 Updated Figure 2: "Safe operating area". Minor text changes 21-Jan-2014 12/13 Changes DocID025498 Rev 5 STF24N60DM2 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved DocID025498 Rev 5 13/13