STF24N60M6
Datasheet
N-channel 600 V, 162 mΩ typ., 17 A, MDmesh™ M6 Power MOSFET
in a TO-220FP package
Features
1
2
3
TO-220FP
Order code
VDS
RDS(on) max.
ID
STF24N60M6
600 V
190 mΩ
17 A
•
•
Reduced switching losses
Lower RDS(on) per area vs previous generation
•
•
•
Low gate input resistance
100% avalanche tested
Zener-protected
D(2)
Applications
•
•
•
G(1)
Switching applications
LLC converters
Boost PFC converters
S(3)
NG1D2S3Z
Product status link
Description
The new MDmesh™ M6 technology incorporates the most recent advancements to
the well-known and consolidated MDmesh family of SJ MOSFETs.
STMicroelectronics builds on the previous generation of MDmesh devices through its
new M6 technology, which combines excellent RDS(on) per area improvement with
one of the most effective switching behaviors available, as well as a user-friendly
experience for maximum end-application efficiency.
STF24N60M6
Product summary
Order code
STF24N60M6
Marking
24N60M6
Package
TO-220FP
Packing
Tube
DS12731 - Rev 1 - August 2018
For further information contact your local STMicroelectronics sales office.
www.st.com
STF24N60M6
Electrical ratings
1
Electrical ratings
Table 1. Absolute maximum ratings
Symbol
Value
Unit
Gate-source voltage
±25
V
Drain current (continuous) at Tcase = 25 °C
17
Drain current (continuous) at Tcase = 100 °C
10.7
IDM(1)
Drain current (pulsed)
52.5
A
PTOT
Total dissipation at Tcase = 25 °C
30
W
dv/dt(2)
Peak diode recovery voltage slope
15
dv/dt(3)
MOSFET dv/dt ruggedness
50
VGS
ID
Parameter
VISO
Insulation withstand voltage (RMS) from all three leads to external heat sink
(t=1s; TC=25 °C)
Tstg
Storage temperature range
Tj
Operating junction temperature range
A
V/ns
2500
V
-55 to 150
°C
Value
Unit
1. Pulse width is limited by safe operating area.
2. ISD ≤ 17 A, di/dt = 400 A/μs, VDS < V(BR)DSS, VDD = 400 V
3. VDS ≤ 480 V
Table 2. Thermal data
Symbol
Parameter
Rthj-case
Thermal resistance junction-case
4.2
°C/W
Rthj-amb
Thermal resistance junction-ambient
62.5
°C/W
Value
Unit
3.2
A
250
mJ
Table 3. Avalanche characteristics
Symbol
IAR
EAS
DS12731 - Rev 1
Parameter
Avalanche current, repetitive or non-repetitive
(pulse width limited by TJmax)
Single pulse avalanche energy
(starting Tj = 25 °C, ID = IAR, VDD = 50 V)
page 2/13
STF24N60M6
Electrical characteristics
2
Electrical characteristics
(Tcase = 25 °C unless otherwise specified).
Table 4. On/off states
Symbol
V(BR)DSS
Parameter
Test conditions
Drain-source breakdown voltage
VGS = 0 V, ID = 1 mA
Min.
Typ.
600
Zero gate voltage drain current
IGSS
1
VGS = 0 V, VDS = 600 V,
Tcase = 125
100
°C(1)
Gate-body leakage current
VDS = 0 V, VGS = ±25 V
VGS(th)
Gate threshold voltage
VDS = VGS, ID = 250 µA
RDS(on)
Static drain-source on-resistance
ID = 8.5 A, VGS = 10 V
Unit
V
VGS = 0 V, VDS = 600 V
IDSS
Max.
µA
±5
µA
4
4.75
V
162
190
mΩ
Min.
Typ.
Max.
Unit
-
960
-
-
76
-
-
4.5
-
3.25
1. Defined by design, not subject to production test.
Table 5. Dynamic
Symbol
Parameter
Test conditions
Ciss
Input capacitance
Coss
Output capacitance
Crss
Reverse transfer capacitance
Coss eq.(1)
Equivalent output capacitance
VDS = 0 to 480 V, VGS = 0 V
-
181
-
pF
RG
Intrinsic gate resistance
f = 1 MHz, ID = 0 A
-
5
-
Ω
Qg
Total gate charge
VDD = 480 V, ID = 17 A,
-
23
-
Qgs
Gate-source charge
VGS = 0 to 10 V
-
4.8
-
Gate-drain charge
(see Figure 14. Test circuit for gate
charge behavior)
-
12.8
-
Qgd
VDS = 100 V, f = 1 MHz, VGS = 0 V
pF
nC
1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0
to 80% VDSS.
Table 6. Switching times
Symbol
td(on)
tr
td(off)
tf
DS12731 - Rev 1
Parameter
Test conditions
Min.
Typ.
Max.
Turn-on delay time
VDD = 300 V, ID = 8.5 A,
-
17.7
-
Rise time
RG = 4.7 Ω, VGS = 10 V
-
32
-
Turn-off delay time
(see Figure 13. Test circuit for
resistive load switching times and
Figure 18. Switching time
waveform)
-
38.3
-
-
9
-
Fall time
Unit
ns
page 3/13
STF24N60M6
Electrical characteristics
Table 7. Source-drain diode
Symbol
ISD
ISDM(1)
(2)
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Source-drain current
-
17
A
Source-drain current (pulsed)
-
52.5
A
1.6
V
Forward on voltage
ISD = 17 A, VGS = 0 V
-
trr
Reverse recovery time
ISD = 17 A, di/dt = 100 A/µs,
-
225
ns
Qrr
Reverse recovery charge
VDD = 60 V
-
2.3
µC
Reverse recovery current
(see Figure 15. Test circuit for
inductive load switching and diode
recovery times)
-
20.4
A
-
387
ns
-
3.85
µC
-
25.1
A
VSD
IRRM
trr
Reverse recovery time
Qrr
Reverse recovery charge
IRRM
Reverse recovery current
ISD = 17 A, di/dt = 100 A/µs,
VDD = 60 V,
Tj = 150 °C
(see Figure 15. Test circuit for
inductive load switching and diode
recovery times)
1. Pulse width is limited by safe operating area.
2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%
DS12731 - Rev 1
page 4/13
STF24N60M6
Electrical characteristics (curves)
2.1
Electrical characteristics (curves)
Figure 2. Thermal impedance
Figure 1. Safe operating area
ID
(A)
GADG060820181621SOA
10 1
tp = 10µs
tp = 100µs
10
tp = 1ms
0
tp = 10ms
Operation in this area is
limited by R DS(on)
10 -1
T j ≤150 °C
T c = 25°C
single pulse
10 -2
10 -1
10 0
10 1
VDS (V)
10 2
Figure 3. Output characteristics
ID
(A)
Figure 4. Transfer characteristics
ID
(A)
GADG200720180952OCH
VGS = 9, 10 V
50
50
VGS = 8 V
40
GADG200720180952TCH
VDS = 16 V
40
30
30
VGS = 7 V
20
20
10
0
0
10
VGS = 6 V
2
4
6
8
10 12 14 16 VDS (V)
Figure 5. Gate charge vs gate-source voltage
VGS
(V)
GADG200720180952QVG VDS
(V)
12
10
600
VDS
500
VDD = 480 V
ID = 17 A
8
7
8
9
VGS (V)
VGS = 10V
170
166
2
100
154
0
Qg (nC)
150
0
16
6
174
200
12
5
GADG010820181133RID
178
4
8
4
RDS(on)
(mΩ)
300
4
3
Figure 6. Static drain-source on-resistance
6
0
0
DS12731 - Rev 1
400
0
2
20
24
162
158
2
4
6
8
10 12 14 16 ID (A)
page 5/13
STF24N60M6
Electrical characteristics (curves)
Figure 7. Capacitance variations
C
(pF)
Figure 8. Output capacitance stored energy
EOSS
(µJ)
10
GADG190720181455CVR
GADG190720181457EOS
9
10 3
CISS
8
7
6
10 2
5
COSS
10
1
10 0
10 -1
f = 1 MHz
CRSS
10 0
10 1
10 2
VDS (V)
Figure 9. Normalized gate threshold voltage vs
temperature
VGS(th)
(norm.)
GADG190720181456VTH
2
1
0
0
100
200
300
400
500
600
VDS (V)
Figure 10. Normalized on-resistance vs temperature
RDS(on)
(norm.)
GADG190720181456RON
VGS = 10 V
1.8
1.0
1.4
0.9
1
0.8
0.6
0.7
0.6
-75
3
2.2
ID = 250 µA
1.1
4
-25
25
75
125
Tj (°C)
Figure 11. Normalized V(BR)DSS vs temperature
V(BR)DSS
(norm.)
GADG190720181457BDV
-25
25
75
125
Tj (°C)
Figure 12. Source-drain diode forward characteristics
VSD
(V)
GADG010820181135SDF
1.1
ID = 1 mA
1.08
0.2
-75
Tj = -50 °C
1
1.04
0.9
Tj = 25 °C
1.00
0.8
0.96
0.92
0.88
-75
DS12731 - Rev 1
Tj = 150 °C
0.7
0.6
-25
25
75
125
Tj (°C)
0.5
0
2
4
6
8
10 12 14 16 ISD (A)
page 6/13
STF24N60M6
Test circuits
3
Test circuits
Figure 13. Test circuit for resistive load switching times
Figure 14. Test circuit for gate charge behavior
VDD
RL
RL
2200
+ μF
3.3
μF
VDD
VD
RG
VGS
IG= CONST
VGS
+
pulse width
D.U.T.
2.7 kΩ
2200
μF
pulse width
D.U.T.
100 Ω
VG
47 kΩ
1 kΩ
AM01469v10
AM01468v1
Figure 15. Test circuit for inductive load switching and
diode recovery times
D
G
A
D.U.T.
S
25 Ω
A
L
A
VD
100 µH
fast
diode
B
B
B
3.3
µF
D
G
+
Figure 16. Unclamped inductive load test circuit
RG
1000
+ µF
2200
+ µF
VDD
3.3
µF
VDD
ID
D.U.T.
S
D.U.T.
Vi
_
pulse width
AM01471v1
AM01470v1
Figure 18. Switching time waveform
Figure 17. Unclamped inductive waveform
ton
V(BR)DSS
td(on)
toff
td(off)
tr
tf
VD
90%
90%
IDM
VDD
10%
0
ID
VDD
AM01472v1
VGS
0
VDS
10%
90%
10%
AM01473v1
DS12731 - Rev 1
page 7/13
STF24N60M6
Package information
4
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK®
packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions
and product status are available at: www.st.com. ECOPACK® is an ST trademark.
DS12731 - Rev 1
page 8/13
STF24N60M6
TO-220FP package information
4.1
TO-220FP package information
Figure 19. TO-220FP package outline
7012510_Rev_12_B
DS12731 - Rev 1
page 9/13
STF24N60M6
TO-220FP package information
Table 8. TO-220FP package mechanical data
Dim.
mm
Min.
Max.
A
4.4
4.6
B
2.5
2.7
D
2.5
2.75
E
0.45
0.7
F
0.75
1
F1
1.15
1.70
F2
1.15
1.70
G
4.95
5.2
G1
2.4
2.7
H
10
10.4
L2
DS12731 - Rev 1
Typ.
16
L3
28.6
30.6
L4
9.8
10.6
L5
2.9
3.6
L6
15.9
16.4
L7
9
9.3
Dia
3
3.2
page 10/13
STF24N60M6
Revision history
Table 9. Document revision history
DS12731 - Rev 1
Date
Version
06-Aug-2018
1
Changes
Initial release.
page 11/13
STF24N60M6
Contents
Contents
1
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2
Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1
Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
4
Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4.1
TO-220FP package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
DS12731 - Rev 1
page 12/13
STF24N60M6
IMPORTANT NOTICE – PLEASE READ CAREFULLY
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Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2018 STMicroelectronics – All rights reserved
DS12731 - Rev 1
page 13/13