STF26N65DM2

STF26N65DM2 Datasheet N-channel 650 V, 0.156 Ω typ., 20 A, MDmesh™ DM2 Power MOSFET in a TO-220FP package Features 1 2 3 TO-220FP D(2) • • • • • • Order code VDS RDS(on) max. ID PTOT STF26N65DM2 650 V 0.190 Ω 20 A 30 W Fast-recovery body diode Extremely low gate charge and input capacitance Low on-resistance 100% avalanche tested Extremely high dv/dt ruggedness Zener-protected Applications G(1) • Switching applications Description S(3) AM15572v1_no_tab This high-voltage N-channel Power MOSFET is part of the MDmesh™ DM2 fastrecovery diode series. It offers very low recovery charge (Qrr) and time (trr) combined with low RDS(on), rendering it suitable for the most demanding high-efficiency converters and ideal for bridge topologies and ZVS phase-shift converters. Product status link STF26N65DM2 Product summary Order code STF26N65DM2 Marking 26N65DM2 Package TO-220FP Packing Tube DS12426 - Rev 2 - July 2018 For further information contact your local STMicroelectronics sales office. www.st.com STF26N65DM2 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol VGS ID(1) Parameter Value Unit Gate-source voltage ±25 V Drain current (continuous) at Tcase = 25 °C 20 Drain current (continuous) at Tcase = 100 °C 12.6 A IDM(2) Drain current (pulsed) 53 A PTOT Total dissipation at Tcase = 25 °C 30 W dv/dt(3) Peak diode recovery voltage slope 50 dv/dt(4) MOSFET dv/dt ruggedness 50 VISO Insulation withstand voltage (RMS) from all three leads to external heatsink (t = 1 s, TC = 25 °C) Tstg Storage temperature range Tj Operating junction temperature range V/ns 2500 V -55 to 150 °C Value Unit 1. Limited by maximum junction temperature 2. Pulse width is limited by safe operating area. 3. ISD ≤ 20 A, di/dt=900 A/μs, VDS peak < V(BR)DSS, VDD = 400 V 4. VDS ≤ 520 V Table 2. Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case 4.2 Rthj-amb Thermal resistance junction-ambient 62.5 °C/W Table 3. Avalanche characteristics Symbol Parameter IAR(1) Avalanche current, repetitive or not repetitive EAS(2) Single pulse avalanche energy Value Unit 3 A 530 mJ 1. Pulse width is limited by TJmax. 2. Starting Tj = 25 °C, ID = IAR, VDD = 50 V DS12426 - Rev 2 page 2/13 STF26N65DM2 Electrical characteristics 2 Electrical characteristics (Tcase = 25 °C unless otherwise specified) Table 4. Static Symbol Parameter Test conditions V(BR)DSS Drain-source breakdown voltage VGS = 0 V, ID = 1 mA Min. Typ. Max. 650 Unit V VGS = 0 V, VDS = 650 V 1 IDSS Zero gate voltage drain current VGS = 0 V, VDS = 650 V, Tcase = 125 °C(1) 100 IGSS Gate-body leakage current VDS = 0 V, VGS = ±25 V ±5 µA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 4 5 V RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 10 A 0.156 0.190 Ω Min. Typ. Max. Unit - 1480 - - 62 - - 2 - 3 µA 1. Defined by design, not subject to production test. Table 5. Dynamic Symbol Parameter Test conditions Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Coss eq.(1) Equivalent output capacitance VDS = 0 to 520 V, VGS = 0 V - 140 - pF RG Intrinsic gate resistance f = 1 MHz, ID = 0 A - 4.6 - Ω Qg Total gate charge VDD = 520 V, ID = 20 A, - 35.5 - Qgs Gate-source charge VGS = 0 to 10 V - 8.2 - Gate-drain charge (see Figure 14. Test circuit for gate charge behavior) - 17.6 - Qgd VDS = 100 V, f = 1 MHz, VGS = 0 V pF nC 1. Coss eq. is defined as the constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. Table 6. Switching times Symbol td(on) tr td(off) tf DS12426 - Rev 2 Parameter Test conditions Min. Typ. Max. Turn-on delay time VDD = 325 V, ID = 10 A, - 17 - Rise time RG = 4.7 Ω, VGS = 10 V - 7 - Turn-off delay time (see Figure 13. Test circuit for resistive load switching times and Figure 18. Switching time waveform) - 51 - - 10 - Fall time Unit ns page 3/13 STF26N65DM2 Electrical characteristics Table 7. Source-drain diode Symbol ISD ISDM(1) (2) Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 20 A Source-drain current (pulsed) - 53 A 1.6 V Forward on voltage VGS = 0 V, ISD = 20 A - trr Reverse recovery time ISD = 20 A, di/dt = 100 A/µs, - 100 ns Qrr Reverse recovery charge VDD = 100 V - 0.365 µC Reverse recovery current (see Figure 15. Test circuit for inductive load switching and diode recovery times) - 7.3 A trr Reverse recovery time ISD = 20 A, di/dt = 100 A/µs, - 200 ns Qrr Reverse recovery charge VDD = 100 V, TJ = 150 °C - 1.39 µC IRRM Reverse recovery current (see Figure 15. Test circuit for inductive load switching and diode recovery times) - 13.9 A VSD IRRM 1. Pulse width is limited by safe operating area. 2. Pulse test: pulse duration = 300 µs, duty cycle 1.5%. DS12426 - Rev 2 page 4/13 STF26N65DM2 Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Figure 2. Thermal impedance Figure 1. Safe operating area ID in this area is (A) Operation limited by R DS(on) GIPG201220170952SOA tp =1 µs 10 1 tp =10 µs tp =100 µs 10 0 tp =1 ms T j ≤150 °C T c = 25°C single pulse 10 -1 10 -1 10 0 tp =10 ms 10 1 VDS (V) 10 2 Figure 3. Output characteristics ID (A) 50 Figure 4. Transfer characteristics ID (A) GIPG201220170957OCH VGS = 8, 9, 10 V VGS = 7 V 40 30 30 VGS = 6 V 20 10 20 10 VGS = 5 V 0 0 5 10 15 20 VDS (V) Figure 5. Gate charge vs gate-source voltage 0 3 RDS(on) (Ω) 600 0.168 10 500 0.164 8 400 0.160 6 300 0.156 4 200 0.152 2 100 0.148 0 Qg (nC) 0.144 0 DS12426 - Rev 2 GIPG201220170958QVG VDS VDD = 520 V ID = 20 A VDS 6 12 18 24 30 36 4 5 6 7 8 VGS (V) Figure 6. Static drain-source on-resistance (V) VGS (V) 0 0 VDS = 20 V 50 40 12 GIPG201220170957TCH GIPG201220170955RID VGS =10 V 4 8 12 16 20 ID (A) page 5/13 STF26N65DM2 Electrical characteristics (curves) Figure 8. Normalized gate threshold voltage vs temperature Figure 7. Capacitance variations C (pF) GIPG201220170957CVR VGS(th) (norm.) 10 4 GIPG201220170954VTH ID = 250 µA 1.1 CISS 10 3 1.0 0.9 10 2 COSS 10 1 f = 1 MHz CRSS 10 10 -1 0 10 0 10 1 VDS (V) 10 2 Figure 9. Normalized on-resistance vs temperature RDS(on) (norm.) GIPG201220170954RON VGS = 10 V 2.2 0.8 0.7 0.6 -75 1.00 1.0 0.96 0.6 0.92 75 125 Tj (°C) Figure 11. Output capacitance stored energy EOSS (µJ) GIPG201220170958EOS 0.88 -75 10 1.0 8 0.9 6 0.8 4 0.7 2 0.6 DS12426 - Rev 2 200 300 ID = 1 mA 400 500 600 VDS (V) -25 25 75 VSD (V) 1.1 100 Tj (°C) 125 Tj (°C) Figure 12. Source-drain diode forward characteristics 12 0 0 125 GIPG201220170955BDV 1.08 1.4 25 75 V(BR)DSS (norm.) 1.04 -25 25 Figure 10. Normalized V(BR)DSS vs temperature 1.8 0.2 -75 -25 0.5 0 GIPG201220170956SDF Tj = -50 °C Tj = 25 °C Tj = 150 °C 4 8 12 16 20 ISD (A) page 6/13 STF26N65DM2 Test circuits 3 Test circuits Figure 13. Test circuit for resistive load switching times Figure 14. Test circuit for gate charge behavior VDD 12 V 2200 + μF 3.3 μF VDD VD VGS 1 kΩ 100 nF RL IG= CONST VGS RG 47 kΩ + pulse width D.U.T. 2.7 kΩ 2200 μF pulse width D.U.T. 100 Ω VG 47 kΩ 1 kΩ AM01469v1 AM01468v1 Figure 15. Test circuit for inductive load switching and diode recovery times D G A D.U.T. S 25 Ω A L A B B 3.3 µF D G + VD 100 µH fast diode B Figure 16. Unclamped inductive load test circuit RG 1000 + µF 2200 + µF VDD 3.3 µF VDD ID D.U.T. S D.U.T. Vi _ pulse width AM01471v1 AM01470v1 Figure 18. Switching time waveform Figure 17. Unclamped inductive waveform ton V(BR)DSS td(on) VD toff td(off) tr tf 90% 90% IDM VDD 10% 0 ID VDD AM01472v1 VGS 0 VDS 10% 90% 10% AM01473v1 DS12426 - Rev 2 page 7/13 STF26N65DM2 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DS12426 - Rev 2 page 8/13 STF26N65DM2 TO-220FP package information 4.1 TO-220FP package information Figure 19. TO-220FP package outline 7012510_Rev_12_B DS12426 - Rev 2 page 9/13 STF26N65DM2 TO-220FP package information Table 8. TO-220FP package mechanical data Dim. mm Min. Max. A 4.4 4.6 B 2.5 2.7 D 2.5 2.75 E 0.45 0.7 F 0.75 1 F1 1.15 1.70 F2 1.15 1.70 G 4.95 5.2 G1 2.4 2.7 H 10 10.4 L2 DS12426 - Rev 2 Typ. 16 L3 28.6 30.6 L4 9.8 10.6 L5 2.9 3.6 L6 15.9 16.4 L7 9 9.3 Dia 3 3.2 page 10/13 STF26N65DM2 Revision history Table 9. Document revision history Date Version 08-Jan-2018 1 Changes First release. Removed maturity status indication from cover page. The document status is production data. 03-Jul-2018 2 Updated Table 6. Switching times. Minor text changes DS12426 - Rev 2 page 11/13 STF26N65DM2 Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4.1 TO-220FP package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 DS12426 - Rev 2 page 12/13 STF26N65DM2 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2018 STMicroelectronics – All rights reserved DS12426 - Rev 2 page 13/13