STF3LN80K5

STF3LN80K5 N-channel 800 V, 2.75 Ω typ., 2 A MDmesh™ K5 Power MOSFET in a TO-220FP package Datasheet - production data Features      TO-220FP Order code VDS RDS(on) max ID STF3LN80K5 800 V 3.25 Ω 2A Industry’s lowest RDS(on) x area Industry’s best FoM (figure of merit) Ultra-low gate charge 100% avalanche tested Zener-protected Applications Figure 1: Internal schematic diagram D(2)  Switching applications Description This very high voltage N-channel Power MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency. G(1) S(3) AM15572v1_no_tab Table 1: Device summary Order code Marking Package Packing STF3LN80K5 3LN80K5 TO-220FP Tube July 2016 DocID027715 Rev 2 This is information on a product in full production. 1/13 www.st.com Contents STF3LN80K5 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 2.1 Electrical characteristics (curves) ................................................ 6 3 Test circuits ..................................................................................... 8 4 Package information ....................................................................... 9 4.1 5 2/13 TO-220FP package information ...................................................... 10 Revision history ............................................................................ 12 DocID027715 Rev 2 STF3LN80K5 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit VGS Gate-source voltage ± 30 V ID(1) Drain current (continuous) at TC = 25 °C 2 A ID(1) Drain current (continuous) at TC = 100 °C 1.25 A ID(2) Drain current (pulsed) 8 A PTOT Total dissipation at TC = 25 °C 20 W VISO Insulation withstand voltage (RMS) from all three leads to external heat sink (t = 1 s; TC = 25 °C) 2500 V dv/dt (3) Peak diode recovery voltage slope 4.5 dv/dt (4) MOSFET dv/dt ruggedness 50 Tstg Storage temperature range Tj Operating junction temperature range V/ns - 55 to 150 °C Notes: (1)Limited (2)Pulse (3)I SD (4)V by maximum junction temperature. width limited by safe operating area. ≤ 2 A, di/dt ≤ 100 A/µs; VDSpeak < V(BR)DSS, VDD = 640 V DS ≤ 640 V. Table 3: Thermal data Symbol Parameter Value Unit Rthj-case Thermal resistance junction-case 6.25 °C/W Rthj-amb Thermal resistance junction-ambient 62.5 °C/W Table 4: Avalanche characteristics Symbol Parameter Value Unit IAR Avalanche current, repetitive or not repetitive (pulse width limited by T jmax) 0.7 A EAS Single pulse avalanche energy (starting Tj = 25°C, ID = IAR; VDD = 50 V) 155 mJ DocID027715 Rev 2 3/13 Electrical characteristics 2 STF3LN80K5 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 5: On /off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage ID = 1 mA, VGS = 0 V Min. Typ. Max. 800 Unit V VDS = 800 V, VGS = 0 V 1 µA VDS = 800 V, VGS = 0 V, TC = 125 °C(1) 50 µA Gate body leakage current VGS = ± 20 V, VGS = 0 V ±10 µA VGS(th) Gate threshold voltage VDS = VGS, ID = 100 µA 4 5 V RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 1 A 2.75 3.25 Ω Min. Typ. Max. Unit - 102 - pF - 11 - pF - 0.1 - pF - 20 - pF - 7 - pF IDSS Zero gate voltage drain current IGSS 3 Notes: (1)Defined by design, not subject to production test. Table 6: Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Cotr(1) Test conditions VDS = 100 V, f = 1 MHz, VGS = 0 V Equivalent capacitance time related VDS = 0 to 640 V, VGS = 0 V Coer(2) Equivalent capacitance energy related RG Intrinsic gate resistance f = 1 MHz, ID = 0 A - 12 - Ω VDD = 640 V, ID = 2 A, VGS = 10 V ( see Figure 15: "Test circuit for gate charge behavior" ) - 2.63 - nC - 0.91 - nC - 1.53 - nC Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge Notes: (1)Time related is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS (2)Energy related is defined as a constant equivalent capacitance giving the same stored energy as C oss when VDS increases from 0 to 80% VDSS 4/13 DocID027715 Rev 2 STF3LN80K5 Electrical characteristics Table 7: Switching times Symbol td(on) Parameter Test conditions VDD = 400 V, ID = 1 A, RG = 4.7 Ω, VGS = 10 V ( see Figure 14: "Test circuit for resistive load switching times" and Figure 19: "Switching time waveform" ) Turn-on delay time tr Rise time td(off) Turn-off delay time tf Fall time Min. Typ. Max. Unit - 6.2 - ns - 7 - ns - 30 - ns - 26 - ns Min. Typ. Max. Unit Table 8: Source drain diode Symbol Parameter Test conditions ISD Source-drain current - 2 A ISDM(1) Source-drain current (pulsed) - 8 A VSD(2) Forward on voltage ISD = 2 A, VGS = 0 V trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current 1.5 V - 210 ns - 0.8 µC - 7.6 A - 345 ns - 1.2 µC - 7.2 A Test conditions Min. Typ. Max. Unit IGS = ± 1 mA, ID = 0 A 30 - - V ISD = 2 A, di/dt = 100 A/µs, VDD = 60 V ( see Figure 16: "Test circuit for inductive load switching and diode recovery times" ) trr - ISD = 2 A, di/dt = 100 A/µs, VDD = 60 V, Tj = 150 °C, (see Figure 16: "Test circuit for inductive load switching and diode recovery times" ) Notes: (1)Pulse width limited by safe operating area. (2)Pulsed: pulse duration = 300 µs, duty cycle 1.5%. Table 9: Gate-source Zener diode Symbol V(BR)GSO Parameter Gate-source breakdown voltage The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection, thus eliminating the need for additional external componentry. DocID027715 Rev 2 5/13 Electrical characteristics 2.1 6/13 STF3LN80K5 2.1 Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance DocID027715 Rev 2 STF3LN80K5 Electrical characteristics Figure 8: Capacitance variations Figure 9: Source-drain diode forward characteristics Figure 10: Normalized gate threshold voltage vs temperature Figure 11: Normalized on-resistance vs temperature Figure 12: Normalized V(BR)DSS vs temperature Figure 13: Maximum avalanche energy vs starting TJ DocID027715 Rev 2 7/13 Test circuits 3 STF3LN80K5 Test circuits Figure 14: Test circuit for resistive load switching times Figure 15: Test circuit for gate charge behavior VDD RL IG= CONST VGS + pulse width 2200 μF 100 Ω D.U.T. 2.7 kΩ VG 47 kΩ 1 kΩ AM01469v10 Figure 16: Test circuit for inductive load switching and diode recovery times Figure 17: Unclamped inductive load test circuit Figure 18: Unclamped inductive waveform 8/13 DocID027715 Rev 2 Figure 19: Switching time waveform STF3LN80K5 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DocID027715 Rev 2 9/13 Package information 4.1 STF3LN80K5 TO-220FP package information Figure 20: TO-220FP package outline 10/13 DocID027715 Rev 2 STF3LN80K5 Package information Table 10: TO-220FP package mechanical data mm Dim. Min. Typ. Max. A 4.4 4.6 B 2.5 2.7 D 2.5 2.75 E 0.45 0.7 F 0.75 1 F1 1.15 1.70 F2 1.15 1.70 G 4.95 5.2 G1 2.4 2.7 H 10 10.4 L2 16 L3 28.6 30.6 L4 9.8 10.6 L5 2.9 3.6 L6 15.9 16.4 L7 9 9.3 Dia 3 3.2 DocID027715 Rev 2 11/13 Revision history 5 STF3LN80K5 Revision history Table 11: Document revision history Date Revision 13-May-2015 1 Initial release 2 Updated title and features in cover page. Updated Table 2: "Absolute maximum ratings" and Section 2: "Electrical characteristics". Added Section 2.1: "2.1 Electrical characteristics (curves)". Minor text changes. 01-Jul-2016 12/13 Changes DocID027715 Rev 2 STF3LN80K5 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved DocID027715 Rev 2 13/13