STF40N65M2

STF40N65M2 N-channel 650 V, 0.087 Ω typ., 32 A MDmesh™ M2 Power MOSFET in a TO-220FP package Datasheet - production data Features 1 2 • • • • 3 Order code VDS RDS(on) max. ID STF40N65M2 650 V 0.099 Ω 32 A Extremely low gate charge Excellent output capacitance (COSS) profile 100% avalanche tested Zener-protected Applications TO-220FP • Figure 1: Internal schematic diagram D(2) Switching applications Description This device is an N-channel Power MOSFET developed using MDmesh™ M2 technology. Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance and optimized switching characteristics, rendering it suitable for the most demanding high efficiency converters. G(1) S(3) AM15572v1_no_tab Table 1: Device summary Order code Marking Package Packaging STF40N65M2 40N65M2 TO-220FP Tube February 2015 DocID027442 Rev 1 This is information on a product in full production. 1/13 www.st.com Contents STF40N65M2 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.2 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package information ....................................................................... 9 4.1 5 2/13 TO-220FP package information ...................................................... 10 Revision history ............................................................................ 12 DocID027442 Rev 1 STF40N65M2 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit ± 25 V VGS Gate-source voltage (1) ID Drain current (continuous) at TC = 25 °C 32 A (1) ID Drain current (continuous) at TC= 100 °C 20 A (2) IDM Drain current (pulsed) 128 A PTOT Total dissipation at TC = 25 °C 25 W dv/dt (3) Peak diode recovery voltage slope 15 V/ns dv/dt (4) MOSFET dv/dt ruggedness 50 V/ns 2500 V - 55 to 150 °C VISO Insulation withstand voltage (RMS) from all three leads to external heat sink (t = 1 s; TC = 25 °C) Tstg Storage temperature Tj Max. operating junction temperature 150 Notes: (1) (2) Limited by maximum junction temperature. Pulse width limited by safe operating area. (3) ISD ≤ 32 A, di/dt ≤ 400 A/µs; VDS peak < V(BR)DSS, VDD = 400 V (4) VDS ≤ 520 V Table 3: Thermal data Symbol Parameter Value Unit Rthj-case Thermal resistance junction-case max 3.13 °C/W Rthj-amb Thermal resistance junction-ambient max 62.50 °C/W Value Unit Table 4: Avalanche characteristics Symbol Parameter IAR Avalanche current, repetetive or not repetetive (pulse width limited by Tjmax) 3 A EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 820 mJ DocID027442 Rev 1 3/13 Electrical characteristics 2 STF40N65M2 Electrical characteristics (TC= 25 °C unless otherwise specified) Table 5: On/off states Symbol Parameter Test conditions V(BR)DSS Drain-source breakdown voltage IDSS Zero gate voltage Drain current IGSS VGS = 0 V, ID = 1 mA Min. Typ. Max. 650 Unit V VGS = 0 V, VDS = 650 V 1 µA VGS = 0 V, VDS = 650 V, TC = 125 °C 100 µA Gate-body leakage current VDS = 0 V, VGS = ± 25 V ±10 µA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 3 4 V RDS(on) Static drain-source onresistance VGS = 10 V, ID = 16 A 0.087 0.099 Ω Min. Typ. Max. Unit - 2355 - pF - 102 - pF - 2.7 - pF 2 Table 6: Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Test conditions VDS= 100 V, f = 1 MHz, VGS = 0 V Equivalent output capacitance VDS = 0 V to 520 V, VGS = 0 V - 380 - pF RG Intrinsic gate resistance f = 1 MHz open drain - 4.5 - Ω Qg Total gate charge - 56.5 - nC Qgs Gate-source charge - 8 - nC Qgd Gate-drain charge - 24 - nC Coss eq. (1) VDD = 520 V, ID = 32 A, VGS = 10 V (see Figure 15: "Gate charge test circuit") Notes: (1) Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS 4/13 DocID027442 Rev 1 STF40N65M2 Electrical characteristics Table 7: Switching times Symbol td(on) tr Parameter Turn-on delay time Rise time td(off) tf Turn-off-delay time Fall time Test conditions Min. Typ. Max. Unit VDD = 325 V, ID = 16 A RG = 4.7 Ω, VGS = 10 V (see Figure 14: "Switching times test circuit for resistive load" and Figure 19: "Switching time waveform") - 15 - ns - 10 - ns - 96.5 - ns - 12 - ns Min. Typ. Max. Unit Table 8: Source drain diode Symbol ISD Parameter Test conditions Source-drain current - 32 A (1) Source-drain current (pulsed) - 128 A (2) Forward on voltage VGS = 0 V, ISD = 32 A - 1.6 V trr Reverse recovery time - 468 ns Qrr Reverse recovery charge - 8.7 µC IRRM Reverse recovery current ISD = 32 A, di/dt = 100 A/µs, VDD = 60 V (see Figure 16: " Test circuit for inductive load switching and diode recovery times") - 37.5 A - 610 ns - 11.7 µC - 39 A ISDM VSD trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ISD = 32 A, di/dt = 100 A/µs, VDD = 60 V, Tj = 150 °C (see Figure 16: " Test circuit for inductive load switching and diode recovery times") Notes: (1) (2) Pulse width is limited by safe operating area Pulse test: pulse duration = 300 µs, duty cycle 1.5% DocID027442 Rev 1 5/13 Electrical characteristics 2.2 STF40N65M2 Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance K GC20521 δ = 0.5 δ = 0.2 δ = 0.1 10-1 10-2 δ = 0.05 δ = 0.02 δ = 0.01 Zth = K*Rthj-c SINGLE PULSE δ = tp / Ƭ tp Ƭ -3 10 VGS = 6,7,8,9,10 V 100 Tp(s) GIPG300120151715ALS 60 50 40 40 30 VGS = 20 V 30 VGS = 4 V 20 20 10 10 4 8 12 16 20 0 0 24 VDS (V) Figure 6: Normalized gate threshold voltage vs temperature 6/13 10-1 70 VGS = 5 V 50 0 0 10-2 ID (A) GIPG300120151500ALS 60 10-3 Figure 5: Transfer characteristics Figure 4: Output characteristics ID (A) 70 10-4 2 4 6 8 VGS (V) Figure 7: Normalized V(BR)DSS vs temperature DocID027442 Rev 1 STF40N65M2 Electrical characteristics Figure 8: Static drain-source on-resistance Figure 9: Normalized on-resistance vs. temperature Figure 10: Gate charge vs. gate-source voltage Figure 11: Capacitance variations Figure 12: Output capacitance stored energy Figure 13: Source-drain diode forward characteristics DocID027442 Rev 1 7/13 Test circuits 3 STF40N65M2 Test circuits Figure 14: Switching times test circuit for resistive load Figure 15: Gate charge test circuit VDD 47 k Ω 12 V 1 kΩ 100 nF I G = CONST Vi ≤ V GS 100 Ω D.U.T. 2.7 k Ω 2200 μ F VG 47 k Ω PW 1 kΩ AM01469v 1 Figure 16: Test circuit for inductive load switching and diode recovery times A A D.U.T. FAST DIODE B B Figure 17: Unclamped inductive load test circuit A D G S 25 Ω L=100 µH 3.3 µF B 1000 µF D G RG VDD D.U.T. S AM01470v1 Figure 18: Unclamped inductive waveform Figure 19: Switching time waveform t on V(BR)DSS t d(on) VD toff tr t d(off) tf 90% 90% I DM 10% ID VDD 10% 0 VDD VGS AM01472v 1 8/13 DocID027442 Rev 1 0 10% VDS 90% AM01473v 1 STF40N65M2 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK is an ST trademark. DocID027442 Rev 1 9/13 Package information 4.1 STF40N65M2 TO-220FP package information Figure 20: TO-220FP package outline 7012510_Rev_K_B 10/13 DocID027442 Rev 1 STF40N65M2 Package information Table 9: TO-220FP mechanical data mm Dim. Min. Typ. Max. A 4.4 4.6 B 2.5 2.7 D 2.5 2.75 E 0.45 0.7 F 0.75 1 F1 1.15 1.70 F2 1.15 1.70 G 4.95 5.2 G1 2.4 2.7 H 10 10.4 L2 16 L3 28.6 30.6 L4 9.8 10.6 L5 2.9 3.6 L6 15.9 16.4 L7 9 9.3 Dia 3 3.2 DocID027442 Rev 1 11/13 Revision history 5 STF40N65M2 Revision history Table 10: Document revision history 12/13 Date Revision 09-Feb-2014 1 DocID027442 Rev 1 Changes First release. STF40N65M2 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved DocID027442 Rev 1 13/13