STF5N105K5

STF5N105K5 N-channel 1050 V, 2.9 Ω typ., 3 A MDmesh™ K5 Power MOSFET in a TO-220FP package Datasheet - production data Features Order code VDS RDS(on) max. ID PTOT STF5N105K5 1050 V 3.5 Ω 3A 25 W     Worldwide best FOM (figure of merit) Ultra low gate charge 100% avalanche tested Zener-protected Applications  Figure 1: Internal schematic diagram Switching applications Description This N-channel Zener-protected Power MOSFET is designed using ST’s revolutionary avalancherugged very high voltage MDmesh™ K5 technology, based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance, and ultra-low gate charge for applications which require superior power density and high efficiency. Table 1: Device summary October 2014 Part number Marking Package Packaging STF5N105K5 5N105K5 TO-220FP Tube DocID026702 Rev 5 This is information on a product in full production. 1/14 www.st.com Contents STF5N105K5 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 9 4 Package mechanical data ............................................................. 10 4.1 5 2/14 TO-220FP package mechanical data .............................................. 11 Revision history ............................................................................ 13 DocID026702 Rev 5 STF5N105K5 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit ± 30 V 3 (1) A Drain current (continuous) at TC = 100 °C 2 (1) A Drain current (pulsed) 12 A Total dissipation at TC = 25 °C 25 W IAR Max current during repetitive or single pulse avalanche 1 A EAS Single pulse avalanche energy (starting TJ = 25 °C, ID=IAS, VDD= 50 V) 85 mJ VISO Insulation withstand voltage (RMS) from all three leads to external heat sink (t=1 s; TC=25 °C) 2500 V Peak diode recovery voltage slope 4.5 V/ns MOSFET dv/dt ruggedness 50 V/ns - 55 to 150 °C VGS Gate- source voltage ID Drain current (continuous) at TC = 25 °C ID IDM (2) PTOT dv/dt (3) dv/dt (4) Tj Operating junction temperature Tstg Storage temperature Notes: (1)Limited (2)Pulse (3)I SD (4)V only by maximum junction temperature width limited by safe operating area. ≤ 3 A, di/dt ≤ 100 A/µs, VDS(peak) ≤ V(BR)DSS DS ≤ 840 V Table 3: Thermal data Symbol Parameter Value Unit Rthj-case Thermal resistance junction-case max 5 °C/W Rthj-amb Thermal resistance junction-amb max 62.5 °C/W DocID026702 Rev 5 3/14 Electrical characteristics 2 STF5N105K5 Electrical characteristics (TCASE = 25 °C unless otherwise specified). Table 4: On/off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage VGS= 0, ID = 1 mA Min. Typ. Max. 1050 Unit V VGS = 0, VDS = 1050 V 1 µA VGS = 0, VDS = 1050 V, Tc=125 °C 50 µA ±10 µA 4 5 V 2.9 3.5 Ω Min. Typ. Max. Unit - 210 - pF - 16 - pF - 0.5 - pF - 26 - pF - 10 - pF IDSS Zero gate voltage drain current IGSS Gate body leakage current VDS = 0, VGS = ± 20 V VGS(th) Gate threshold voltage VDS = VGS, ID = 100 µA RDS(on) Static drain-source onresistance VGS = 10 V, ID= 1.5 A 3 Table 5: Dynamic Symbol Parameter Test conditions Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Co(tr)(1) Equivalent capacitance time related VGS=0, VDS =100 V, f=1 MHz VGS = 0, VDS = 0 to 840 V Co(er)(2) Equivalent capacitance energy related RG Intrinsic gate resistance f = 1MHz open drain - 9 - Ω Qg Total gate charge - 12.5 - nC Qgs Gate-source charge - 2 - nC Qgd Gate-drain charge VDD = 840 V, ID = 3 A VGS =10 V Figure 16: "Gate charge test circuit" - 9.5 - nC Notes: (1)Time related is defined as a constant equivalent capacitance giving the same charging time as C oss when VDS increases from 0 to 80% VDSS (2)energy related is defined as a constant equivalent capacitance giving the same stored energy as C oss when VDS increases from 0 to 80% VDSS Table 6: Switching times Symbol td(on) tr td(off) tf 4/14 Parameter Turn-on delay time Rise time Turn-off delay time Test conditions VDD = 525V, ID = 1.5 A, RG=4.7 Ω, VGS=10 V Figure 18: " Unclamped inductive load test circuit" Fall time DocID026702 Rev 5 Min. Typ. Max. Unit - 15.5 - ns - 8.5 - ns - 31 - ns - 24 - ns STF5N105K5 Electrical characteristics Table 7: Source drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit ISD Source-drain current - 3 A ISDM Source-drain current (pulsed) - 12 A VGS=0, ISD= 3 A - 1.5 V ISD= 3 A, VDD= 60 V di/dt = 100 A/µs, Figure 17: " Test circuit for inductive load switching and diode recovery times" - 400 ns - 2.3 µC - 12 A ISD= 3 A,VDD= 60 V di/dt=100 A/µs, Tj=150 °C Figure 17: " Test circuit for inductive load switching and diode recovery times" - 560 ns - 3.1 µC - 11 VSD(1) Forward on voltage trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current A Notes: (1)Pulsed: pulse duration = 300µs, duty cycle 1.5% Table 8: Gate-source Zener diode Symbol V(BR)GSO Parameter Gate-source breakdown voltage Test conditions IGS = ± 1mA, ID=0 Min Typ. Max. Unit 30 - - V The built-in back-to-back Zener diodes have specifically been designed to enhance the device's ESD capability. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device's integrity. These integrated Zener diodes thus avoid the usage of external components. DocID026702 Rev 5 5/14 Electrical characteristics 2.1 STF5N105K5 Electrical characteristics (curves) Figure 3: Thermal impedance Figure 2: Safe operating area GC20940 K 10 -1 10 -2 10 -3 10 -4 10 -3 10 -2 10 -1 10 0 T p(s) Figure 5: Transfer characteristics Figure 4: Output characteristics GIPG290820141204FSR GIPG290820141334FSR ID (A) ID(A) V DS=20V 6 5 V GS=10, 11V 5 4 9V 4 3 3 8V 2 2 1 1 7V 6V 0 0 5 10 15 20 Figure 6: Gate charge vs gate-source voltage GIPG290820141348FSR V DS V GS (V) 10 0 5 V DS(V) V DS=840V ID=3A 1200 8 800 6 600 4 400 2 200 7 9 8 10 V GS(V) Figure 7: Static drain-source on-resistance (V) V DS 6 GIPG290820141400FSR R DS(on) (Ω) V GS=10V 4 3.5 3 2.5 2 1.5 0 0 6/14 2 4 6 8 10 12 0 Q g(nC) DocID026702 Rev 5 1 0 1 2 3 4 ID(A) STF5N105K5 Electrical characteristics Figure 8: Capacitance variations GIPG290820141409FSR C (pF) Figure 9: Maximum avalanche energy GIPG290820141445FSR E AS (mJ) 80 1000 70 Ciss 100 60 50 40 10 Coss Crss 1 30 20 10 0.1 0.1 1 100 10 V DS(V) Figure 10: Normalized gate threshold voltage vs temperature 0 0 20 40 60 80 100 120 140 T J(°C) Figure 11: Normalized on-resistance vs temperature AM18082v1 V GS(th) (norm) ID=100 µ A 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 0.4 -100 -50 0 50 100 150 T J(°C) Figure 12: Normalized V(BR)DSS vs temperature Figure 13: Source-drain diode forward characteristics AM18083v1 V (BR)DSS (norm) GIPG290820141432FSR V SD (V) ID=1m A 1.1 1 1.05 0.9 1 T J=-50°C T J=25°C 0.8 0.95 0.7 0.9 0.6 T J=150°C 0.85 -100 -50 0 50 100 T J(°C) DocID026702 Rev 5 0.5 0 0.5 1 1.5 2 2.5 3 ISD(A) 7/14 Electrical characteristics STF5N105K5 Figure 14: Output capacitance stored energy vs temperature GIPG290820141419FSR E oss (µJ) 4 2 0 0 8/14 200 400 600 DocID026702 Rev 5 800 V DS(V) STF5N105K5 3 Test circuits Test circuits Figure 15: Switching times test circuit for resistive load Figure 17: Test circuit for inductive load switching and diode recovery times Figure 19: Unclamped inductive waveform DocID026702 Rev 5 Figure 16: Gate charge test circuit Figure 18: Unclamped inductive load test circuit Figure 20: Switching time waveform 9/14 Package mechanical data 4 STF5N105K5 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 10/14 DocID026702 Rev 5 STF5N105K5 4.1 Package mechanical data TO-220FP package mechanical data Figure 21: TO-220FP package outline DocID026702 Rev 5 11/14 Package mechanical data STF5N105K5 Table 9: TO-220FP mechanical data mm Dim. Min. Max. A 4.4 4.6 B 2.5 2.7 D 2.5 2.75 E 0.45 0.7 F 0.75 1 F1 1.15 1.70 F2 1.15 1.70 G 4.95 5.2 G1 2.4 2.7 H 10 10.4 L2 12/14 Typ. 16 L3 28.6 30.6 L4 9.8 10.6 L5 2.9 3.6 L6 15.9 16.4 L7 9 9.3 Dia 3 3.2 DocID026702 Rev 5 STF5N105K5 5 Revision history Revision history Table 10: Document revision history Date Revision Changes 17-Jul-2014 1 First release. 01-Sep-2014 2 Document status promoted from preliminary to production data. Inserted Section 3.1: "Electrical characteristics (curves)". Minor text changes. 02-Sep-2014 3 Updated title in cover page. 03-Oct-2014 4 Updated: Figure 3: "Thermal impedance", Figure 6: "Gate charge vs gate-source voltage" and Figure 8: "Capacitance variations" 15-Oct-2014 5 Updated Table 2: "Absolute maximum ratings" DocID026702 Rev 5 13/14 STF5N105K5 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2014 STMicroelectronics – All rights reserved 14/14 DocID026702 Rev 5