STF5N60M2

STF5N60M2 N-channel 600 V, 1.3 Ω typ., 3.5 A MDmesh™ M2 Power MOSFET in a TO-220FP package Datasheet - production data Features Order code VDS@ TJmax RDS(on) max. ID STF5N60M2 650 V 1.4 Ω 3.5 A     Extremely low gate charge Excellent output capacitance (COSS) profile 100% avalanche tested Zener-protected Applications TO-220FP  Figure 1: Internal schematic diagram Switching applications Description This device is an N-channel Power MOSFET developed using MDmesh™ M2 technology. Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance and optimized switching characteristics, rendering it suitable for the most demanding high efficiency converters. Table 1: Device summary Order code Marking Package Packing STF5N60M2 5N60M2 TO-220FP Tube June 2016 DocID025320 Rev 2 This is information on a product in full production. 1/13 www.st.com Contents STF5N60M2 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package information ....................................................................... 9 4.1 5 2/13 TO-220FP package information ...................................................... 10 Revision history ............................................................................ 12 DocID025320 Rev 2 STF5N60M2 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit Gate-source voltage ±25 V Drain current (continuous) at TC = 25 °C 3.5 Drain current (continuous) at TC = 100 °C 2.2 IDM(2) Drain current (pulsed) 14 A PTOT Total dissipation at TC = 25 °C 20 W VISO Insulation withstand voltage (RMS) from all three leads to external heat sink (t = 1 s; TC = 25 °C) 2500 V VGS ID(1) dv/dt (3) Peak diode recovery voltage slope 15 dv/dt (4) MOSFET dv/dt ruggedness 50 Tstg Storage temperature range Tj Operating junction temperature range A V/ns -55 to 150 °C Value Unit Notes: (1)Limited by package. (2) Pulse width limited by safe operating area. (3) ISD ≤ 3.5 A, di/dt ≤ 400 A/μs; VDS peak < V(BR)DSS, VDD = 400 V. (4) VDS ≤ 480 V. Table 3: Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case max. 6.25 °C/W Rthj-amb Thermal resistance junction-ambient max. 62.5 °C/W Value Unit Table 4: Avalanche characteristics Symbol Parameter IAR Avalanche current, repetitive or not repetitive (pulse width limited by Tjmax) 0.5 A EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR; VDD = 50 V) 80 mJ DocID025320 Rev 2 3/13 Electrical characteristics 2 STF5N60M2 Electrical characteristics (Tcase = 25 °C unless otherwise specified) Table 5: On /off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage VGS = 0 V, ID = 1 mA Min. Typ. Max. 600 Unit V VGS = 0 V, VDS = 600 V 1 VGS = 0 V, VDS = 600 V, TC = 125 °C (1) 100 Gate-body leakage current VDS = 0 V, VGS = ±25 V ±10 μA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 3 4 V RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 1.7 A 1.3 1.4 Ω Min. Typ. Max. Unit - 211 - - 13 - - 0.75 - IDSS Zero gate voltage drain current IGSS 2 µA Notes: (1) Defined by design, not subject to production test. Table 6: Dynamic Symbol Parameter Test conditions Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Coss eq.(1) Equivalent output capacitance VDS = 0 to 480 V, VGS = 0 V - 19.5 - pF RG Intrinsic gate resistance f = 1 MHz open drain - 6.2 - Ω Qg Total gate charge - 8 - Qgs Gate-source charge - 1.6 - Qgd Gate-drain charge VDD = 480 V, ID = 3.5 A, VGS = 10 V (see Figure 15: "Test circuit for gate charge behavior") - 4.4 - VDS = 100 V, f = 1 MHz, VGS = 0 V pF nC Notes: (1) Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. Table 7: Switching times Symbol td(on) Turn-on delay time tr Rise time td(off) Turn-off delay time tf 4/13 Parameter Test conditions VDD = 300 V, ID = 1.7 A RG = 4.7 Ω, VGS = 10 V (see Figure 14: "Test circuit for resistive load switching times" and Figure 19: "Switching time waveform") Fall time DocID025320 Rev 2 Min. Typ. Max. - 12 - - 3 - - 70 - - 15 - Unit ns STF5N60M2 Electrical characteristics Table 8: Source-drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit ISD Source-drain current - 3.5 A ISDM(1) Source-drain current (pulsed) - 14 A VSD(2) Forward on voltage - 1.6 V trr VGS = 0 V, ISD = 3.5 A Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ISD = 3.5 A, di/dt = 100 A/µs, VDD = 60 V (see Figure 16: "Test circuit for inductive load switching and diode recovery times") trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ISD = 3.5 A, di/dt = 100 A/µs, VDD = 60 V, Tj = 150 °C (see Figure 16: "Test circuit for inductive load switching and diode recovery times") - 220 ns - 1.05 µC - 9.5 A - 314 ns - 1.5 µC - 9.5 A Notes: (1) Pulse width is limited by safe operating area. (2) Pulse test: pulse duration = 300 µs, duty cycle 1.5 %. DocID025320 Rev 2 5/13 Electrical characteristics 2.1 6/13 STF5N60M2 Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance DocID025320 Rev 2 STF5N60M2 Electrical characteristics Figure 8: Capacitance variations Figure 9: Output capacitance stored energy Figure 10: Normalized gate threshold voltage vs temperature Figure 11: Normalized on-resistance vs temperature Figure 12: Normalized V(BR)DSS vs temperature Figure 13: Source- drain diode forward characteristics DocID025320 Rev 2 7/13 Test circuits 3 STF5N60M2 Test circuits Figure 15: Test circuit for gate charge behavior Figure 14: Test circuit for resistive load switching times Figure 16: Test circuit for inductive load switching and diode recovery times Figure 17: Unclamped inductive load test circuit Figure 18: Unclamped inductive waveform 8/13 DocID025320 Rev 2 Figure 19: Switching time waveform STF5N60M2 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DocID025320 Rev 2 9/13 Package information 4.1 STF5N60M2 TO-220FP package information Figure 20: TO-220FP package outline 10/13 DocID025320 Rev 2 STF5N60M2 Package information Table 9: TO-220FP package mechanical data mm Dim. Min. Typ. Max. A 4.4 4.6 B 2.5 2.7 D 2.5 2.75 E 0.45 0.7 F 0.75 1 F1 1.15 1.70 F2 1.15 1.70 G 4.95 5.2 G1 2.4 2.7 H 10 10.4 L2 16 L3 28.6 30.6 L4 9.8 10.6 L5 2.9 3.6 L6 15.9 16.4 L7 9 9.3 Dia 3 3.2 DocID025320 Rev 2 11/13 Revision history 5 STF5N60M2 Revision history Table 10: Document revision history Date Revision 30-Sep-2013 1 First release. 2 Updated title, features and description in cover page. Updated Section 1: "Electrical ratings" and Section 2: "Electrical characteristics". Added Section 2.1: "Electrical characteristics (curves)". Minor text changes. 15-Jun-2016 12/13 Changes DocID025320 Rev 2 STF5N60M2 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved DocID025320 Rev 2 13/13