STF7LN80K5

STF7LN80K5 N-channel 800 V, 0.95 Ω typ., 5 A MDmesh™ K5 Power MOSFET in a TO-220FP package Datasheet - production data Features 1 2 • • • • • 3 TO-220FP Order code VDS RDS(on) max. ID STF7LN80K5 800 V 1.15 Ω 5A Industry’s lowest RDS(on) x area Industry’s best figure of merit (FoM) Ultra-low gate charge 100% avalanche tested Zener-protected Applications Figure 1: Internal schematic diagram D(2) • Switching applications Description This very high voltage N-channel Power MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency. G(1) S(3) AM15572v1_no_tab Table 1: Device summary Order code Marking Package Packing STF7LN80K5 7LN80K5 TO-220FP Tube January 2016 DocID028769 Rev 2 This is information on a product in full production. 1/13 www.st.com Contents STF7LN80K5 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package information ....................................................................... 9 4.1 5 2/13 TO-220FP package information ...................................................... 10 Revision history ............................................................................ 12 DocID028769 Rev 2 STF7LN80K5 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol VGS Parameter Gate-source voltage Value Unit ± 30 V ID Drain current (continuous) at TC = 25 °C 5 A (1) ID Drain current (continuous) at TC = 100 °C 3.4 A (2) ID Drain current (pulsed) 20 A PTOT Total dissipation at TC = 25 °C 25 W VISO Insulation withstand voltage (RMS) from all three leads to external heat sink (t=1 s; TC=25 °C) 2500 V (1) dv/dt (3) Peak diode recovery voltage slope 4.5 dv/dt (4) MOSFET dv/dt ruggedness 50 Tstg Storage temperature range TJ Operating junction temperature range V/ns - 55 to 150 °C Notes: (1) (2) Limited by maximum junction temperature Pulse width limited by safe operating area (3) ISD ≤ 5 A, di/dt 100 A/μs; VDS peak < V(BR)DSS,VDD= 640 V (4) VDS ≤ 640 V Table 3: Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case Rthj-amb Thermal resistance junction-ambient Value Unit 5 °C/W 62.5 °C/W Value Unit Table 4: Avalanche characteristics Symbol Parameter IAR Avalanche current, repetitive or not repetitive (pulse width limited by Tjmax) 1.5 A EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 200 mJ DocID028769 Rev 2 3/13 Electrical characteristics 2 STF7LN80K5 Electrical characteristics TC = 25 °C unless otherwise specified Table 5: On/off-state Symbol V(BR)DSS Parameter Drain-source breakdown voltage Test conditions Min. VGS = 0 V, ID = 1 mA 800 Typ. Max. Unit V VGS = 0 V, VDS = 800 V 1 µA IDSS Zero gate voltage drain current VGS = 0 V, VDS = 800 V TC = 125 °C 50 µA IGSS Gate body leakage current VDS = 0 V, VGS = ±20 V ±10 µA VGS(th) Gate threshold voltage VDS = VGS, ID = 100 µA 4 5 V RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 2.5 A 0.95 1.15 Ω Min. Typ. Max. Unit - 270 - pF - 22 - pF - 0.5 - pF - 17 - nC - 48 3 Table 6: Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance (1) Co(er) (2) Co(tr) Test conditions VDS = 100 V, f = 1 MHz, VGS = 0 V Equivalent capacitance energy related Equivalent capacitance time related VDS = 0 to 640 V, VGS = 0 V nC Rg Intrinsic gate resistance f = 1 MHz, ID=0 A - 7.5 - Ω Qg Total gate charge - 12 - nC Qgs Gate-source charge - 2.6 - nC Qgd Gate-drain charge VDD = 640 V, ID = 5 A VGS= 10 V See (Figure 15: "Test circuit for gate charge behavior") - 8.6 - nC Notes: (1) Energy related is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS increases from 0 to 80% VDSS (2) Time related is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS increases from 0 to 80% VDSS Table 7: Switching times Symbol td(on) tr td(off) tf 4/13 Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions Min. Typ. Max. Unit VDD= 400 V, ID =2.5 A, RG = 4.7 Ω VGS = 10 V See (Figure 14: "Test circuit for resistive load switching times" and Figure 19: "Switching time waveform") - 9.3 - ns - 6.7 - ns - 23.6 - ns - 17.4 - ns DocID028769 Rev 2 STF7LN80K5 Electrical characteristics Table 8: Source-drain diode Symbol ISD Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 5 A (1) Source-drain current (pulsed) - 20 A (2) Forward on voltage ISD = 5 A, VGS = 0 V - 1.6 V trr Reverse recovery time - 276 ns Qrr Reverse recovery charge - 2.13 µC IRRM Reverse recovery current ISD = 5 A, di/dt = 100 A/µs,VDD = 60 V See Figure 16: "Test circuit for inductive load switching and diode recovery times" - 15.4 A - 402 ns - 2.79 µC - 13.9 A ISDM VSD trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ISD = 5 A, di/dt = 100 A/µs VDD = 60 V, Tj = 150 °C See Figure 16: "Test circuit for inductive load switching and diode recovery times" Notes: (1) (2) Pulse width limited by safe operating area Pulsed: pulse duration = 300 µs, duty cycle 1.5% Table 9: Gate-source Zener diode Symbol V(BR)GSO Parameter Gate-source breakdown voltage Test conditions IGS= ± 1mA, ID= 0 A Min. Typ. Max. Unit 30 - - V The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection,thus eliminating the need for additional external componentry. DocID028769 Rev 2 5/13 Electrical characteristics 2.2 STF7LN80K5 Electrical characteristics (curves) Figure 3: Thermal impedance Figure 2: Safe operating area 6/13 Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance DocID028769 Rev 2 STF7LN80K5 Electrical characteristics Figure 8: Capacitance variations Figure 9: Normalized gate threshold voltage vs temperature Figure 10: Normalized V(BR)DSS vs temperature Figure 11: Normalized on-resistance vs temperature Figure 12: Source-drain diode forward characteristics Figure 13: Maximum avalanche energy vs starting TJ DocID028769 Rev 2 7/13 Test circuits 3 8/13 STF7LN80K5 Test circuits Figure 14: Test circuit for resistive load switching times Figure 15: Test circuit for gate charge behavior Figure 16: Test circuit for inductive load switching and diode recovery times Figure 17: Unclamped inductive load test circuit Figure 18: Unclamped inductive waveform Figure 19: Switching time waveform DocID028769 Rev 2 STF7LN80K5 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK is an ST trademark. DocID028769 Rev 2 9/13 Package information 4.1 STF7LN80K5 TO-220FP package information Figure 20: TO-220FP package outline 7012510_Rev_K_B 10/13 DocID028769 Rev 2 STF7LN80K5 Package information Table 10: TO-220FP package mechanical data mm Dim. Min. Typ. Max. A 4.4 4.6 B 2.5 2.7 D 2.5 2.75 E 0.45 0.7 F 0.75 1 F1 1.15 1.70 F2 1.15 1.70 G 4.95 5.2 G1 2.4 2.7 H 10 10.4 L2 16 L3 28.6 30.6 L4 9.8 10.6 L5 2.9 3.6 L6 15.9 16.4 L7 9 9.3 Dia 3 3.2 DocID028769 Rev 2 11/13 Revision history 5 STF7LN80K5 Revision history Table 11: Document revision history 12/13 Date Revision Changes 20-Jan-2016 1 First release. 25-Jan-2016 2 Updated: Figure 3: "Thermal impedance" Minor text changes DocID028769 Rev 2 STF7LN80K5 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved DocID028769 Rev 2 13/13