STF7N105K5

STF7N105K5 N-channel 1050 V, 1.4 Ω typ., 4 A MDmesh™ K5 Power MOSFET in TO-220FP package Datasheet - production data Features Order code STF7N105K5      TO-220FP V DS RDS(on) max. ID PTOT 2.0 Ω 4A 25 W 1050 V Industry’s lowest RDS(on) x area Industry’s best FoM (figure of merit) Ultra-low gate charge 100% avalanche tested Zener-protected Applications Figure 1: Internal schematic diagram D(2)  Switching applications Description This very high voltage N-channel Power MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency. G(1) S(3) AM15572v1_no_tab Table 1: Device summary Order code Marking Package Packaging STF7N105K5 7N105K5 TO-220FP Tube June 2016 DocID026184 Rev 2 This is information on a product in full production. 1/14 www.st.com Contents STF7N105K5 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 9 4 Package information ..................................................................... 10 4.1 5 2/14 TO-220FP package information ...................................................... 11 Revision history ............................................................................ 13 DocID026184 Rev 2 STF7N105K5 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter VGS ID Value Unit Gate- source voltage ± 30 V Drain current (continuous) at TC = 25 °C 4(1) A A Drain current (continuous) at TC = 100 °C 3(1) IDM(2) Drain current (pulsed) 16 A PTOT Total dissipation at TC = 25 °C 25 W IAR Max. current during repetitive or single pulse avalanche 1.5 A EAS Single pulse avalanche energy (starting TJ = 25 °C, ID=IAR, VDD= 50 V) 132 mJ VISO Insulation withstand voltage (RMS) from all three leads to external heat sink (t = 1 s; TC = 25 °C) 2500 V Peak diode recovery voltage slope 4.5 V/ns MOSFET dv/dt ruggedness 50 V/ns - 55 to 150 °C ID dv/dt (3) dv/dt (4) Tj Operating junction temperature range Tstg Storage temperature range Notes: (1)Limited (2)Pulse (3)I SD (4)V by package. width limited by safe operating area. ≤ 4 A, di/dt ≤ 100 A/µs, VDS(peak) ≤ V(BR)DSS ; VSD ≤ 840 V DS ≤ 840 V Table 3: Thermal data Symbol Parameter Value Unit Rthj-case Thermal resistance junction-case max 5 °C/W Rthj-amb Thermal resistance junction-amb max 62.5 °C/W DocID026184 Rev 2 3/14 Electrical characteristics 2 STF7N105K5 Electrical characteristics (TCASE = 25 °C unless otherwise specified). Table 4: On/off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage VGS= 0 V, ID = 1 mA Min. Typ. Max. 1050 Unit V VGS = 0 V, VDS = 1050 V 1 µA VGS = 0 V, VDS = 1050 V, TC=125 °C(1) 50 µA Gate body leakage current VDS = 0, VGS = ± 20 V ±10 µA VGS(th) Gate threshold voltage VDS = VGS, ID = 100 µA 4 5 V RDS(on) Static drain-source onresistance VGS = 10 V, ID= 2 A 1.4 2 Ω Min. Typ. Max. Unit - 380 - pF - 40 - pF - 0.65 - pF - 47 - pF - 17 - pF IDSS Zero gate voltage drain current IGSS 3 Notes: (1)Defined by design, not subject to production test. Table 5: Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Co(tr)(1) Test conditions VDS =100 V, f=1 MHz, VGS=0 V Equivalent capacitance time related VGS = 0 V, VDS = 0 to 840 V Co(er)(2) Equivalent capacitance energy related RG Intrinsic gate resistance f = 1MHz open drain - 7 - Ω Qg Total gate charge - 11 - nC Qgs Gate-source charge - 2.8 - nC Qgd Gate-drain charge VDD = 840 V, ID = 4 A VGS =10 V Figure 16: "Test circuit for gate charge behavior" - 5.6 - nC Notes: (1)Time related is defined as a constant equivalent capacitance giving the same charging time as C oss when VDS increases from 0 to 80% VDSS (2)Energy related is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS increases from 0 to 80% VDSS 4/14 DocID026184 Rev 2 STF7N105K5 Electrical characteristics Table 6: Switching times Symbol td(on) tr td(off) tf Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions Min. Typ. Max. Unit VDD = 525 V, ID = 2 A, RG=4.7 Ω, VGS=10 V (see Figure 15: "Test circuit for resistive load switching times" and Figure 20: "Switching time waveform") - 17.5 - ns - 7 - ns - 43 - ns - 25 - ns Min. Typ. Max. Unit 4 A 16 A 1.6 V Table 7: Source drain diode Symbol Parameter Test conditions ISD Source-drain current ISDM Source-drain current (pulsed) - VSD(1) Forward on voltage ISD= 4 A, VGS=0 - trr Reverse recovery time - 370 ns Qrr Reverse recovery charge - 3 µC IRRM Reverse recovery current ISD= 4 A, VDD= 60 V di/dt = 100 A/µs, Figure 17: "Test circuit for inductive load switching and diode recovery times" - 16.5 A ISD= 4 A,VDD= 60 V di/dt=100 A/µs, Tj=150 °C Figure 17: "Test circuit for inductive load switching and diode recovery times" - 600 ns - 4.4 µC - 14.5 A trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current Notes: (1)Pulsed: pulse duration = 300µs, duty cycle 1.5% Table 8: Gate-source Zener diode Symbol V(BR)GSO Parameter Gate-source breakdown voltage Test conditions IGS = ± 1mA, ID=0 Min Typ. Max. Unit 30 - - V The built-in back-to-back Zener diodes have been specifically designed to enhance the ESD capability of the device. The Zener voltage is appropriate for efficient and costeffective intervention to protect the device integrity. These integrated Zener diodes thus eliminate the need for external components. DocID026184 Rev 2 5/14 Electrical characteristics 2.1 STF7N105K5 Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance Ω 6/14 DocID026184 Rev 2 STF7N105K5 Electrical characteristics Figure 8: Capacitance variations Figure 9: Source-drain diode forward characteristics Figure 10: Normalized gate threshold voltage vs temperature Figure 11: Normalized on-resistance vs temperature µ Figure 12: Normalized V(BR)DSS vs temperature Figure 13: Maximum avalanche energy vs starting Tj GIPG210320141421S A EAS (mJ) 120 ID=1.5 A VDD=50 V 100 80 60 40 20 0 0 DocID026184 Rev 2 20 40 60 80 100 120 140 TJ(°C) 7/14 Electrical characteristics STF7N105K5 Figure 14: Output capacitance stored energy µ 8/14 DocID026184 Rev 2 STF7N105K5 3 Test circuits Test circuits Figure 16: Test circuit for gate charge behavior Figure 15: Test circuit for resistive load switching times Figure 17: Test circuit for inductive load switching and diode recovery times Figure 18: Unclamped inductive load test circuit Figure 19: Unclamped inductive waveform DocID026184 Rev 2 Figure 20: Switching time waveform 9/14 Package information 4 STF7N105K5 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 10/14 DocID026184 Rev 2 STF7N105K5 4.1 Package information TO-220FP package information Figure 21: TO-220FP package outline DocID026184 Rev 2 11/14 Package information STF7N105K5 Table 9: TO-220FP package mechanical data mm Dim. Min. Max. A 4.4 4.6 B 2.5 2.7 D 2.5 2.75 E 0.45 0.7 F 0.75 1 F1 1.15 1.70 F2 1.15 1.70 G 4.95 5.2 G1 2.4 2.7 H 10 10.4 L2 12/14 Typ. 16 L3 28.6 30.6 L4 9.8 10.6 L5 2.9 3.6 L6 15.9 16.4 L7 9 9.3 Dia 3 3.2 DocID026184 Rev 2 STF7N105K5 5 Revision history Revision history Table 10: Document revision history Date Revision Changes 07-Apr-2014 1 First release. 07-Jun-2016 2 Updated Figure 6: "Gate charge vs gate-source voltage" and Table 5: "Dynamic". Minor text changes. DocID026184 Rev 2 13/14 STF7N105K5 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved 14/14 DocID026184 Rev 2