STF7N52DK3

STD7N52DK3, STF7N52DK3 Datasheet N-channel 525 V, 0.95 Ω typ., 6 A, SuperFREDmesh3™ Power MOSFETs in DPAK and TO-220FP packages Features Order codes STD7N52DK3 TAB 3 2 1 TO-220FP DPAK 1 2 STF7N52DK3 3 D(2, TAB) G(1) • • • • • • VDS RDS(on) max. ID 525 V 1.15 Ω 6A PTOT 90 W 25 W 100% avalanche tested Extremely high dv/dt capability Gate charge minimized Very low intrinsic capacitance Improved diode reverse recovery characteristics Zener-protected Applications • S(3) AM01475V1 Switching applications Description These devices are developed using the revolutionary N-channel SuperFREDmesh3™ technology. They associate all advantages of reduced onresistance, Zener gate protection and very high dv/dt capability with a fast body-drain recovery diode. Such series complements the FDmesh™ advanced technology. Product status links STD7N52DK3 STF7N52DK3 Product summary STD7N52DK3 Order code STD7N52DK3 Marking 7N52DK3 Package DPAK Packing Tape and reel STF7N52DK3 Order code STF7N52DK3 Marking 7N52DK3 Package TO-220FP Packing Tube DS6515 - Rev 3 - October 2018 For further information contact your local STMicroelectronics sales office. www.st.com STD7N52DK3, STF7N52DK3 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Parameter Value DPAK TO-220FP Unit VDS Drain-source voltage 525 V VGS Gate-source voltage ±30 V Drain current (continuous) at TC = 25 °C 6 6(1) A 4 4(1) A Drain current (pulsed) 24 24(1) A PTOT Total dissipation at TC = 25 °C 90 25 W IAR(3) Avalanche current, repetitive or non-repetitive ID IDM Drain current (continuous) at TC = 100 °C (2) (4) 3 A EAS Single pulse avalanche energy 110 mJ dv/dt(5) Peak diode recovery voltage slope 20 V/ns di/dt(5) Diode reverse recovery current slope 400 A/ns Insulation withstand voltage (RMS) from all three leads to external heat sink VISO 2.5 kV (t = 1 s, TC = 25 °C) Tstg Storage temperature range TJ -55 to 150 Operating junction temperature range °C 1. This value is limited by maximum junction temperature. 2. Pulse width is limited by safe operating area. 3. Pulse width is limited by TJmax. 4. Starting TJ = 25 °C, ID = IAR, VDD = 50 V 5. ISD ≤ 6 A, VDS(peak) ≤ V(BR)DSS, VDD = 80% V(BR)DSS Table 2. Thermal data Symbol Rthj-case Rthj-pcb (1) Rthj-amb Parameter Value DPAK TO-220FP Thermal resistance junction-case 1.39 5 Thermal resistance junction-pcb 50 Thermal resistance junction-ambient Unit °C/W °C/W 62.5 °C/W 1. When mounted on an 1-inch² FR-4, 2oz Cu board. DS6515 - Rev 3 page 2/19 STD7N52DK3, STF7N52DK3 Electrical characteristics 2 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 3. On/off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage Min. ID = 1 mA, VGS = 0 V Typ. 525 Zero gate voltage drain current IGSS Gate body leakage current VGS = ±20 V, VDS = 0 V VGS(th) Gate threshold voltage VDS = VGS, ID = 50 µA RDS(on) Static drain-source onresistance VGS = 10 V, ID = 3 A VGS = 0 V, VDS = 525 V, TC = 125 1 µA 50 µA ±10 µA 3.75 4.5 V 0.95 1.15 Ω Typ. Max. Unit - pF °C(1) 3 Unit V VGS = 0 V, VDS = 525 V IDSS Max. 1. Defined by design, not subject to production test. Table 4. Dynamic Symbol Parameter Test conditions Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Coss(tr)(1) Time-related equivalent output capacitance Coss(er)(2) 870 VDS = 50 V, f = 1 MHz, VGS = 0 V - 70 13 Energy-related equivalent output capacitance - 53 - pF - 74 - pF - 3.5 - Ω - nC VDS = 0 to 420 V, VGS = 0 V RG Intrinsic gate resistance f = 1 MHz open drain Qg Total gate charge VDD = 420 V, ID = 6 A, Qgs Gate-source charge VGS = 0 to 10 V Gate-drain charge (see Figure 17. Test circuit for gate charge behavior) Qgd Min. 33 - 5 19 1. Coss(tr) is defined as the constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 420 V. 2. Coss(er). is defined as the constant equivalent capacitance giving the same stored energy as Coss when VDS increases from 0 to 420 V. Table 5. Switching times Symbol td(on) tr td(off) tf DS6515 - Rev 3 Parameter Test conditions Turn-on delay time VDD = 260 V, ID = 3 A, Rise time RG = 4.7 Ω, VGS = 10 V Turn-off delay time (see Figure 16. Test circuit for resistive load switching times and Figure 21. Switching time waveform) Fall time Min. Typ. Max. Unit - ns 12 12 - 37 19 page 3/19 STD7N52DK3, STF7N52DK3 Electrical characteristics Table 6. Source-drain diode Symbol ISD Parameter Test conditions Source-drain current Typ. Source-drain current (pulsed) VSD(2) Forward on voltage ISD = 6 A, VGS = 0 V trr Reverse recovery time ISD = 6 A, di/dt = 100 A/µs, Qrr Reverse recovery charge VDD = 60 V Reverse recovery current (see Figure 18. Test circuit for inductive load switching and diode recovery times) trr Reverse recovery time ISD = 6 A, di/dt = 100 A/µs, Qrr Reverse recovery charge VDD = 60 V, Tj = 150 °C IRRM Reverse recovery current (see Figure 18. Test circuit for inductive load switching and diode recovery times) 24 - - - Max. 6 - ISDM(1) IRRM Min. 1.5 Unit A V 110 ns 0.44 μC 8 A 140 ns 0.68 μC 10 A 1. Pulse width limited by safe operating area. 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%. Table 7. Gate-source Zener diode Symbol V(BR)GSO Parameter Gate-source breakdown voltage Test conditions IGS = ±1 mA, ID = 0 A Min. Typ. Max. Unit 30 - - V The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection, thus eliminating the need for additional external componentry. DS6515 - Rev 3 page 4/19 STD7N52DK3, STF7N52DK3 Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Figure 1. Safe operating area for DPAK AM07185v1 ID (A) Figure 2. Thermal impedance for DPAK GC20460 K 10µs 10 100µs DS (o n ) Op Lim e ra ite tio n d by in th m is ax ar R ea is 100 1 1ms 10ms Tj=150°C 0.1 0.1 Tc=25°C S ingle puls e 10 1 10-1 100 VDS (V) Figure 3. Safe operating area for TO-220FP AM07186v1 ID (A) 10-2 10-5 10-4 10-3 10-2 tp (s) 10-1 Figure 4. Thermal impedance for TO-220FP K GC20940 on ) 10µs S( O p Li e ra m ite tio n d by in t m h is ax a R D re a is 10 1 10 -1 100µs 1ms 10ms 0.1 10 -2 Tj=150°C Tc=25°C S ingle puls e 0.01 0.1 10 1 VDS (V) 100 Figure 5. Output characteristics AM07188v1 ID (A) VGS =10V 7V 12 10 -2 10 -1 t p (s) 10 0 Figure 6. Transfer characteristics AM07189v1 ID (A) VDS =20V 12 10 10 8 8 6 6 6V 4 4 2 2 0 10 -3 14 14 DS6515 - Rev 3 10 -3 10 -4 5V 0 5 10 15 20 25 VDS (V) 0 0 1 2 3 4 5 6 7 8 9 VGS (V) page 5/19 STD7N52DK3, STF7N52DK3 Electrical characteristics (curves) Figure 7. Gate charge vs gate-source voltage AM07190v1 VGS (V) 12 400 VDD=420V ID=6A VDS VDS (V) 450 350 10 300 Figure 8. Static drain-source on-resistance 1.06 1.04 1.00 250 0.98 6 200 0.96 150 0.94 100 0.92 2 0 10 0 30 20 50 0.90 0 Q g (nC) 0.88 Figure 9. Capacitance variations 0 1 2 3 4 5 6 ID(A) Figure 10. Output capacitance stored energy AM07192v1 C (pF) VGS =10V 1.02 8 4 AM07191v1 R DS (on) (Ω) AM07193v1 E os s (µJ ) 4.0 1000 Cis s 3.5 3.0 2.5 100 2.0 10 Cos s 1.5 Crs s 1.0 0.5 1 0.1 1 100 10 VDS (V) Figure 11. Normalized gate threshold voltage vs temperature AM07194v1 VGS (th) (norm) 1.10 0 0 100 200 300 400 500 VDS (V) Figure 12. Normalized on-resistance vs temperature AM07195v1 R DS (on) (norm) 2.5 2.0 1.00 1.5 0.90 1.0 0.80 0.70 -75 DS6515 - Rev 3 0.5 -25 25 75 125 TJ (°C) 0.0 -75 -25 25 75 125 TJ (°C) page 6/19 STD7N52DK3, STF7N52DK3 Electrical characteristics (curves) Figure 14. Normalized V(BR)DSS vs temperature Figure 13. Source-drain diode forward characteristics AM07198v1 VS D (V) 1.0 V(BR)DSS (norm) TJ =-50°C AM07196v1 1.10 0.9 1.05 0.8 TJ =25°C 0.7 TJ =150°C 1.00 0.6 0.95 0.5 0.4 0 10 20 30 40 0.90 -75 50 IS D(A) -25 25 75 125 TJ (°C) Figure 15. Maximum avalanche energy vs starting TJ AM07197v1 E AS (mJ ) ID=3 A VDD=50 V 110 100 90 80 70 60 50 40 30 20 10 0 0 DS6515 - Rev 3 20 40 60 80 100 120 140 TJ (°C) page 7/19 STD7N52DK3, STF7N52DK3 Test circuits 3 Test circuits Figure 16. Test circuit for resistive load switching times Figure 17. Test circuit for gate charge behavior VDD 12 V 2200 + μF 3.3 μF VDD VD VGS 1 kΩ 100 nF RL IG= CONST VGS RG 47 kΩ + pulse width D.U.T. 2.7 kΩ 2200 μF pulse width D.U.T. 100 Ω VG 47 kΩ 1 kΩ AM01469v1 AM01468v1 Figure 18. Test circuit for inductive load switching and diode recovery times D G A D.U.T. S 25 Ω A L A B B 3.3 µF D G + VD 100 µH fast diode B Figure 19. Unclamped inductive load test circuit RG 1000 + µF 2200 + µF VDD 3.3 µF VDD ID D.U.T. S D.U.T. Vi _ pulse width AM01471v1 AM01470v1 Figure 21. Switching time waveform Figure 20. Unclamped inductive waveform ton V(BR)DSS td(on) VD toff td(off) tr tf 90% 90% IDM VDD 10% 0 ID VDD AM01472v1 VGS 0 VDS 10% 90% 10% AM01473v1 DS6515 - Rev 3 page 8/19 STD7N52DK3, STF7N52DK3 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DS6515 - Rev 3 page 9/19 STD7N52DK3, STF7N52DK3 DPAK (TO-252) type A2 package information 4.1 DPAK (TO-252) type A2 package information Figure 22. DPAK (TO-252) type A2 package outline 0068772_type-A2_rev25 DS6515 - Rev 3 page 10/19 STD7N52DK3, STF7N52DK3 DPAK (TO-252) type A2 package information Table 8. DPAK (TO-252) type A2 mechanical data Dim. mm Min. Max. A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 b 0.64 0.90 b4 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 D 6.00 6.20 D1 4.95 E 6.40 E1 5.10 5.20 5.30 e 2.159 2.286 2.413 e1 4.445 4.572 4.699 H 9.35 10.10 L 1.00 1.50 L1 2.60 2.80 3.00 L2 0.65 0.80 0.95 L4 0.60 R V2 DS6515 - Rev 3 Typ. 5.10 5.25 6.60 1.00 0.20 0° 8° page 11/19 STD7N52DK3, STF7N52DK3 DPAK (TO-252) type A2 package information Figure 23. DPAK (TO-252) recommended footprint (dimensions are in mm) FP_0068772_25 DS6515 - Rev 3 page 12/19 STD7N52DK3, STF7N52DK3 DPAK (TO-252) packing information 4.2 DPAK (TO-252) packing information Figure 24. DPAK (TO-252) tape outline 10 pitches cumulative tolerance on tape +/- 0.2 mm T P0 Top cover tape P2 D E F B1 K0 For machine ref. only including draft and radii concentric around B0 W B0 A0 P1 D1 User direction of feed R Bending radius User direction of feed AM08852v1 DS6515 - Rev 3 page 13/19 STD7N52DK3, STF7N52DK3 DPAK (TO-252) packing information Figure 25. DPAK (TO-252) reel outline T 40mm min. access hole at slot location B D C N A G measured at hub Tape slot in core for tape start 2.5mm min.width Full radius AM06038v1 Table 9. DPAK (TO-252) tape and reel mechanical data Tape Dim. mm mm Dim. Min. Max. A0 6.8 7 A B0 10.4 10.6 B 1.5 12.1 C 12.8 1.6 D 20.2 G 16.4 50 B1 DS6515 - Rev 3 Reel Min. Max. 330 13.2 D 1.5 D1 1.5 E 1.65 1.85 N F 7.4 7.6 T K0 2.55 2.75 P0 3.9 4.1 Base qty. 2500 P1 7.9 8.1 Bulk qty. 2500 P2 1.9 2.1 R 40 T 0.25 0.35 W 15.7 16.3 18.4 22.4 page 14/19 STD7N52DK3, STF7N52DK3 TO-220FP package information 4.3 TO-220FP package information Figure 26. TO-220FP package outline 7012510_Rev_12_B DS6515 - Rev 3 page 15/19 STD7N52DK3, STF7N52DK3 TO-220FP package information Table 10. TO-220FP package mechanical data Dim. mm Min. Max. A 4.4 4.6 B 2.5 2.7 D 2.5 2.75 E 0.45 0.7 F 0.75 1 F1 1.15 1.70 F2 1.15 1.70 G 4.95 5.2 G1 2.4 2.7 H 10 10.4 L2 DS6515 - Rev 3 Typ. 16 L3 28.6 30.6 L4 9.8 10.6 L5 2.9 3.6 L6 15.9 16.4 L7 9 9.3 Dia 3 3.2 page 16/19 STD7N52DK3, STF7N52DK3 Revision history Table 11. Document revision history Date Version Changes 09-Oct-2009 1 First release 20-Oct-2010 2 Document status promoted from preliminary data to datasheet The part number STP7N52DK3 has been moved to a separate datasheet and the document has been updated accordingly. 01-Oct-2018 3 Updated Section 4 Package information. Minor text changes DS6515 - Rev 3 page 17/19 STD7N52DK3, STF7N52DK3 Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4.1 DPAK (TO-252) type A2 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 DPAK (TO-252) packing information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.3 TO-220FP package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 DS6515 - Rev 3 page 18/19 STD7N52DK3, STF7N52DK3 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2018 STMicroelectronics – All rights reserved DS6515 - Rev 3 page 19/19