STF7N60DM2
N-channel 600 V, 0.78 Ω typ., 6 A MDmesh™ DM2
Power MOSFET in a TO-220FP package
Datasheet - production data
Features
Order code
VDS
RDS(on) max.
ID
PTOT
STF7N60DM2
600 V
0.90 Ω
6A
25 W
TO-220FP
Figure 1: Internal schematic diagram
D(2)
Fast-recovery body diode
Extremely low gate charge and input
capacitance
Low on-resistance
100% avalanche tested
Extremely high dv/dt ruggedness
Zener-protected
Applications
Switching applications
Description
This high voltage N-channel Power MOSFET is
part of the MDmesh™ DM2 fast recovery diode
series. It offers very low recovery charge (Qrr)
and time (trr) combined with low RDS(on), rendering
it suitable for the most demanding high efficiency
converters and ideal for bridge topologies and
ZVS phase-shift converters.
G(1)
S(3)
AM15572v1_no_tab
Table 1: Device summary
Order code
Marking
Package
Packing
STF7N60DM2
7N60DM2
TO-220FP
Tube
June 2017
DocID030790 Rev 1
This is information on a product in full production.
1/13
www.st.com
Contents
STF7N60DM2
Contents
1
Electrical ratings ............................................................................. 3
2
Electrical characteristics ................................................................ 4
2.1
Electrical characteristics (curves) ...................................................... 6
3
Test circuits ..................................................................................... 8
4
Package information ....................................................................... 9
4.1
5
2/13
TO-220FP package information ...................................................... 10
Revision history ............................................................................ 12
DocID030790 Rev 1
STF7N60DM2
1
Electrical ratings
Electrical ratings
Table 2: Absolute maximum ratings
Symbol
VGS
Parameter
Gate-source voltage
Value
Unit
±25
V
Drain current (continuous) at Tcase = 25 °C
6
Drain current (continuous) at Tcase = 100 °C
3.8
IDM(1)
Drain current (pulsed)
24
A
PTOT
W
ID
A
Total dissipation at Tcase = 25 °C
25
dv/dt(2)
Peak diode recovery voltage slope
50
dv/dt(3)
MOSFET dv/dt ruggedness
50
VISO
Insulation withstand voltage (RMS) from all three leads to
external heat sink (t = 1 s; TC = 25 °C)
2.5
kV
Tstg
Storage temperature range
-55 to 150
°C
Value
Unit
Tj
Operating junction temperature range
V/ns
Notes:
(1)
Pulse width is limited by safe operating area.
(2)
ISD ≤ 6 A, di/dt=900 A/μs; VDS peak < V(BR)DSS, VDD = 480 V.
(3)
VDS ≤ 480 V.
Table 3: Thermal data
Symbol
Parameter
Rthj-case
Thermal resistance junction-case
5
Rthj-amb
Thermal resistance junction-amb
62.5
°C/W
Table 4: Avalanche characteristics
Symbol
IAR(1)
EAS(2)
Parameter
Value
Unit
Avalanche current, repetitive or not repetitive
1.5
A
Single pulse avalanche energy
160
mJ
Notes:
(1)
Pulse width limited by Tjmax.
(2)
Starting Tj = 25 °C, ID = IAR, VDD = 50 V.
DocID030790 Rev 1
3/13
Electrical characteristics
2
STF7N60DM2
Electrical characteristics
(Tcase = 25 °C unless otherwise specified)
Table 5: Static
Symbol
Parameter
Test conditions
V(BR)DSS
Drain-source breakdown
voltage
VGS = 0 V, ID = 1 mA
Min.
Typ.
Max.
600
Unit
V
VGS = 0 V, VDS = 600 V
1
VGS = 0 V, VDS = 600 V,
Tcase = 125 °C (1)
100
Gate-body leakage
current
VDS = 0 V, VGS = ±25 V
±5
µA
VGS(th)
Gate threshold voltage
VDS = VGS, ID = 250 µA
4
4.75
V
RDS(on)
Static drain-source
on-resistance
VGS = 10 V, ID = 3 A
0.78
0.90
Ω
Min.
Typ.
Max.
Unit
-
324
-
-
18
-
-
2
-
IDSS
Zero gate voltage drain
current
IGSS
3.25
µA
Notes:
(1)Defined
by design, not subject to production test.
Table 6: Dynamic
Symbol
Parameter
Ciss
Input capacitance
Coss
Output capacitance
Crss
Reverse transfer
capacitance
Coss
Test conditions
VDS = 100 V, f = 1 MHz,
VGS = 0 V
pF
Equivalent output
capacitance
VDS = 0 to 480 V, VGS = 0 V
-
25
-
pF
RG
Intrinsic gate resistance
f = 1 MHz, ID = 0 A
-
6
-
Ω
Qg
Total gate charge
-
7.5
-
Qgs
Gate-source charge
-
2.2
-
Qgd
Gate-drain charge
VDD = 480 V, ID = 6 A,
VGS = 0 to 10 V
(see Figure 15: "Test circuit for
gate charge behavior")
-
3.2
-
eq.
(1)
nC
Notes:
(1)
Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS
increases from 0 to 80% VDSS.
Table 7: Switching times
Symbol
td(on)
tr
td(off)
tf
4/13
Parameter
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Test conditions
Min.
Typ.
Max.
VDD = 300 V, ID = 3 A
RG = 4.7 Ω, VGS = 10 V
(see Figure 14: "Test circuit for
resistive load switching times"
and Figure 19: "Switching time
waveform")
-
10
-
-
6
-
-
12.6
-
-
22.6
-
DocID030790 Rev 1
Unit
ns
STF7N60DM2
Electrical characteristics
Table 8: Source-drain diode
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
ISD
Source-drain current
-
6
A
ISDM(1)
Source-drain current
(pulsed)
-
24
A
VSD(2)
Forward on voltage
-
1.6
V
VGS = 0 V, ISD = 6 A
trr
Reverse recovery time
Qrr
Reverse recovery
charge
IRRM
Reverse recovery
current
trr
Reverse recovery time
Qrr
Reverse recovery
charge
IRRM
Reverse recovery
current
ISD = 6 A, di/dt = 100 A/µs,
VDD = 60 V
(see Figure 16: "Test circuit for
inductive load switching and
diode recovery times")
ISD = 6 A, di/dt = 100 A/µs,
VDD = 60 V, Tj = 150 °C
(see Figure 16: "Test circuit for
inductive load switching and
diode recovery times")
-
69
ns
-
164
nC
-
4.8
A
-
144
ns
-
492
nC
-
6.8
A
Notes:
(1)
Pulse width is limited by safe operating area.
(2)
Pulse test: pulse duration = 300 µs, duty cycle 1.5%.
DocID030790 Rev 1
5/13
Electrical characteristics
2.1
STF7N60DM2
Electrical characteristics (curves)
Figure 2: Safe operating area
Figure 3: Thermal impedance
Figure 4: Output characteristics
Figure 5: Transfer characteristics
Figure 6: Gate charge vs gate-source voltage
Figure 7: Static drain-source on-resistance
6/13
DocID030790 Rev 1
STF7N60DM2
Electrical characteristics
Figure 8: Capacitance variations
Figure 9: Output capacitance stored energy
Figure 10: Normalized gate threshold voltage vs
temperature
Figure 11: Normalized on-resistance vs temperature
Figure 12: Source-drain diode forward
characteristics
Figure 13: Normalized V(BR)DSS vs temperature
DocID030790 Rev 1
7/13
Test circuits
3
8/13
STF7N60DM2
Test circuits
Figure 14: Test circuit for resistive load
switching times
Figure 15: Test circuit for gate charge
behavior
Figure 16: Test circuit for inductive load
switching and diode recovery times
Figure 17: Unclamped inductive load test
circuit
Figure 18: Unclamped inductive waveform
Figure 19: Switching time waveform
DocID030790 Rev 1
STF7N60DM2
4
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
DocID030790 Rev 1
9/13
Package information
4.1
STF7N60DM2
TO-220FP package information
Figure 20: TO-220FP package outline
7012510_Rev_12_B
10/13
DocID030790 Rev 1
STF7N60DM2
Package information
Table 9: TO-220FP package mechanical data
mm
Dim.
Min.
Typ.
Max.
A
4.4
4.6
B
2.5
2.7
D
2.5
2.75
E
0.45
0.7
F
0.75
1
F1
1.15
1.70
F2
1.15
1.70
G
4.95
5.2
G1
2.4
2.7
H
10
10.4
L2
16
L3
28.6
30.6
L4
9.8
10.6
L5
2.9
3.6
L6
15.9
16.4
L7
9
9.3
Dia
3
3.2
DocID030790 Rev 1
11/13
Revision history
5
STF7N60DM2
Revision history
Table 10: Document revision history
12/13
Date
Revision
20-Jun-2017
1
DocID030790 Rev 1
Changes
First release.
STF7N60DM2
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DocID030790 Rev 1
13/13
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