STF7N90K5

STF7N90K5 Datasheet N-channel 900 V, 0.72 Ω typ., 7 A, MDmesh™ K5 Power MOSFET in a TO-220FP package Features 1 2 3 TO-220FP Order code VDS RDS(on ) max. ID STF7N90K5 900 V 0.81 Ω 7A • Industry’s lowest RDS(on) x area • • • • Industry’s best FoM (figure of merit) Ultra-low gate charge 100% avalanche tested Zener-protected D(2) Applications • Switching applications G(1) Description S(3) AM01476v1_No_tab This very high voltage N-channel Power MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency. Product status STF7N90K5 Product summary Order code STF7N90K5 Marking 7N90K5 Package TO-220FP Packing Tube DS11868 - Rev 2 - February 2018 For further information contact your local STMicroelectronics sales office. www.st.com STF7N90K5 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol VGS Parameter Gate-source voltage Value Unit ±30 V ID Drain current (continuous) at TC = 25 °C 7 A ID Drain current (continuous) at TC = 100 °C 4.4 A ID(1) Drain current (pulsed) 28 A PTOT Total dissipation at TC = 25 °C 25 W VISO Insulation withstand voltage (RMS) from all three leads to external heat sink (t = 1 s, TC = 25 °C) 2500 V dv/dt(2) Peak diode recovery voltage slope 4.5 dv/dt(3) MOSFET dv/dt ruggedness 50 Tj Tstg Operating junction temperature range Storage temperature range V/ns -55 to 150 °C Value Unit 5 °C/W 62.5 °C/W Value Unit 1. Pulse width limited by safe operating area 2. ISD ≤ 7 A, di/dt ≤ 100 A/μs, VDS peak < V(BR)DSS, VDD = 450 V 3. VDS ≤ 720 V Table 2. Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case Rthj-amb Thermal resistance junction-ambient Table 3. Avalanche characteristics Symbol DS11868 - Rev 2 Parameter IAR Avalanche current, repetitive or not repetitive (pulse width limited by Tjmax) 2.4 A EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 230 mJ page 2/13 STF7N90K5 Electrical characteristics 2 Electrical characteristics TC = 25 °C unless otherwise specified Table 4. On-/off-state Symbol Parameter Test conditions Min. V(BR)DSS Drain-source breakdown voltage VGS = 0 V, ID = 1 mA 900 Typ. Zero gate voltage drain current 1 µA 50 µA ±10 µA 4 5 V 0.72 0.81 Ω Min. Typ. Max. Unit - 425 - pF - 41 - pF - 1.2 - pF - 64 - pF VGS = 0 V, VDS = 900 V TC = 125 °C (1) IGSS Gate body leakage current VDS = 0 V, VGS = ±20 V VGS(th) Gate threshold voltage VDD = VGS, ID = 100 µA RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 3.5 A Unit V VGS = 0 V, VDS = 900 V IDSS Max. 3 1. Defined by design, not subject to production test. Table 5. Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Co(tr)(1) Co(er)(2) Time-related equivalent capacitance Energy-related equivalent capacitance Test conditions VDS = 100 V, f = 1 MHz, VGS = 0 V VGS = 0, VDS = 0 to 720 V 24 pF Rg Intrinsic gate resistance f = 1 MHz , ID = 0 A - 6.7 - Ω Qg Total gate charge VDD = 720 V, ID = 7 A - 12 - nC Qgs Gate-source charge VGS = 0 to 10 V - 3.5 - nC Gate-drain charge (see Figure 14. Test circuit for gate charge behavior) - 6.5 - nC Qgd 1. Co(tr) is a constant capacitance value that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS. 2. Co(er) is a constant capacitance value that gives the same stored energy as Coss while VDS is rising from 0 to 80% VDSS. Table 6. Switching times Symbol td(on) tr td(off) tf DS11868 - Rev 2 Parameter Test conditions Min. Typ. Max. Unit Turn-on delay time VDD = 450 V, ID = 3.5 A, - 13.2 - ns Rise time RG = 4.7 Ω, VGS = 10 V - 14.2 - ns Turn-off delay time (see Figure 13. Test circuit for resistive load switching times and Figure 18. Switching time waveform) - 31.6 - ns - 14.7 - ns Fall time page 3/13 STF7N90K5 Electrical characteristics Table 7. Source-drain diode Symbol ISD ISDM(1) (2) Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 7 A Source-drain current (pulsed) - 28 A 1.5 V Forward on voltage ISD = 7 A, VGS = 0 V - trr Reverse recovery time ISD = 7 A, di/dt = 100 A/µs, - 352 ns Qrr Reverse recovery charge VDD = 60 V - 3.63 µC Reverse recovery current (see Figure 15. Test circuit for inductive load switching and diode recovery times) - 20.6 A trr Reverse recovery time ISD = 7 A, di/dt = 100 A/µs, - 525 ns Qrr Reverse recovery charge VDD = 60 V, Tj = 150 °C - 4.94 µC IRRM Reverse recovery current (see Figure 15. Test circuit for inductive load switching and diode recovery times) - 18.8 A VSD IRRM 1. Pulse width limited by safe operating area 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5% Table 8. Gate-source Zener diode Symbol Parameter Test conditions Min. Typ. Max. Unit V(BR)GSO Gate-source breakdown voltage IGS= ±1 mA, ID= 0 A ±30 - - V The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection, thus eliminating the need for additional external componentry. DS11868 - Rev 2 page 4/13 STF7N90K5 Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Figure 1. Safe operating area ID (A) 10 1 Figure 2. Thermal impedance K GADG111020161307SOA Operation in this area is limited by R DS(on) GC20940 10 -1 tp= 10 µs 10 0 tp= 100µs 10 -2 tp= 1 ms 10 tp= 10 ms -1 single pulse T j ≤150 °C T c = 25 °C 10 -2 10 -1 10 0 10 1 10 2 10 3 V DS (V) 10 -3 10 -4 Figure 3. Output characteristics ID (A) 10 -3 10 -2 10 -1 10 0 t p (s) Figure 4. Transfer characteristics ID (A) GIPG051020161339OCH GIPG051020161340TCH V DS =20 V VGS = 11 V 15 15 VGS = 10 V 10 10 VGS = 9 V VGS = 8 V 5 5 VGS = 7 V VGS = 6 V 0 0 4 8 12 16 V DS (V) Figure 5. Gate charge vs gate-source voltage VGS (V) GIPG051020161340QVG VDS (V) VDS 14 500 8 400 4 300 Qgd Qgs DS11868 - Rev 2 8 9 10 V GS (V) Figure 6. Static drain-source on-resistance GIPG051020161341RID R DS(on) [Ω] V GS =10 V 0.8 0.7 200 2 0 0 7 600 10 6 6 700 VDD = 720 V ID = 7 A 12 0 5 100 2 4 6 8 10 12 14 0 Qg (nC) 0.6 0 2 4 6 I D (A) page 5/13 STF7N90K5 Electrical characteristics (curves) Figure 7. Capacitance variations C (pF) GIPG051020161342CVR V GS(th) (norm.) 1000 100 Figure 8. Normalized gate threshold voltage vs temperature GIPG051020161343VTH I D = 100 µA 1.2 C ISS 1 f =1 MHz C OSS 0.8 0.6 10 C RSS 0.4 1 0.1 1 10 100 V DS (V) Figure 9. Normalized on-resistance vs temperature R DS(on) (norm.) GIPG051020161344RON 2.6 V GS = 10 V 0.2 -50 V (BR)DSS (norm.) 1.8 1.04 1.4 1.00 1 0.96 0.6 0.92 50 100 T j (°C) Figure 11. Maximum avalanche energy vs starting TJ EAS (mJ) GADG061020160850EAS 100 T j (°C) GIPG051020161345BDV 1.12 1.08 0 50 Figure 10. Normalized V(BR)DSS vs temperature 2.2 0.2 -50 0 I D = 1 mA 0.88 -50 0 50 100 T j (°C) Figure 12. Source-drain diode forward characteristics V SD (V) GADG071020160858SDF 1 Single pulse ID =2.4 A,VDD =50 V T j = -50 °C 0.9 200 0.8 0.7 100 T j = 25 °C T j = 150 °C 0.6 0 -50 DS11868 - Rev 2 0 50 100 TJ (°C) 0.5 1 2 3 4 5 6 I SD (A) page 6/13 STF7N90K5 Test circuits 3 Test circuits Figure 13. Test circuit for resistive load switching times Figure 14. Test circuit for gate charge behavior VDD RL RL 2200 + μF 3.3 μF VDD VD + pulse width RG VGS IG= CONST VGS 2.7 kΩ 2200 μF D.U.T. D.U.T. 100 Ω VG 47 kΩ pulse width 1 kΩ AM01469v10 AM01468v1 Figure 15. Test circuit for inductive load switching and diode recovery times Figure 16. Unclamped inductive load test circuit L D G A D.U.T. S 25 Ω A A 100 µH fast diode B B B VD 3.3 µF D G + RG 1000 + µF 2200 + µF 3.3 µF VDD ID VDD D.U.T. S D.U.T. Vi _ pulse width AM01471v1 AM01470v1 Figure 17. Unclamped inductive waveform Figure 18. Switching time waveform V(BR)DSS VD ton td(on) IDM toff td(off) tr 90% 90% 10% ID VDD tf VDD 10% 0 VGS AM01472v1 0 VDS 90% 10% AM01473v1 DS11868 - Rev 2 page 7/13 STF7N90K5 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DS11868 - Rev 2 page 8/13 STF7N90K5 TO-220FP package information 4.1 TO-220FP package information Figure 19. TO-220FP package outline 7012510_Rev_12_B DS11868 - Rev 2 page 9/13 STF7N90K5 TO-220FP package information Table 9. TO-220FP package mechanical data Dim. mm Min. Max. A 4.4 4.6 B 2.5 2.7 D 2.5 2.75 E 0.45 0.7 F 0.75 1 F1 1.15 1.70 F2 1.15 1.70 G 4.95 5.2 G1 2.4 2.7 H 10 10.4 L2 DS11868 - Rev 2 Typ. 16 L3 28.6 30.6 L4 9.8 10.6 L5 2.9 3.6 L6 15.9 16.4 L7 9 9.3 Dia 3 3.2 page 10/13 STF7N90K5 Revision history Table 10. Document revision history Date Revision 11-Oct-2016 1 Changes First release. Removed maturity status indication from cover page. The document status is production data. Updated Table 5. Dynamic. 21-Feb-2018 2 Updated Figure 5. Gate charge vs gate-source voltage. Updated Section 4.1 TO-220FP package information. Minor text changes DS11868 - Rev 2 page 11/13 STF7N90K5 Contents Contents 1 Electrical ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics (curves). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.1 TO-220FP package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 DS11868 - Rev 2 page 12/13 STF7N90K5 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2018 STMicroelectronics – All rights reserved DS11868 - Rev 2 page 13/13