STF8NM50N
N-channel 500 V, 0.73 Ω, 5 A MDmesh™II Power MOSFET
in TO-220FP
Features
Order codes
VDSS@TJMAX RDS(on)max.
STF8NM50N
550 V
ID
< 0.79 Ω
5A
■
100% avalanche tested
■
Low input capacitances and gate charge
■
Low gate input resistance
3
1
Applications
■
2
TO-220FP
Switching applications
Description
This device is an N-channel Power MOSFET
developed using the second generation of
MDmesh™ technology. This revolutionary Power
MOSFET associates a vertical structure to the
company’s strip layout to yield one of the world’s
lowest on-resistance and gate charge. It is
therefore suitable for the most demanding high
efficiency converters.
Figure 1.
Internal schematic diagram
$
'
3
!-V
Table 1.
Device summary
Order codes
Marking
Packages
Packaging
STF8NM50N
8NM50N
TO-220FP
Tube
November 2011
Doc ID 022505 Rev 2
1/12
www.st.com
12
Contents
STF8NM50N
Contents
1
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
Test circuits
4
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2/12
.............................................. 8
Doc ID 022505 Rev 2
STF8NM50N
1
Electrical ratings
Electrical ratings
Table 2.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
VDS
Drain-source voltage
500
V
VGS
Gate-source voltage
± 25
V
(1)
A
Drain current (continuous) at TC = 25 °C
ID
5
Total dissipation at TC = 25 °C
20
W
Peak diode recovery voltage slope
15
V/ns
2500
V
- 55 to 150
°C
150
°C
Value
Unit
Rthj-case Thermal resistance junction-case max
6.25
°C/W
Rthj-amb Thermal resistance junction-ambient max
62.5
°C/W
300
°C
PTOT
dv/dt
(2)
VISO
Insulation withstand voltage (RMS) from all
three leads to external heat sink
(t = 1 s; TC = 25 °C)
Tstg
Storage temperature
Tj
Max. operating junction temperature
1. Limited by maximum junction temperature.
2. ISD ≤ 7 A, di/dt ≤ 400 A/µs, VPeak < V(BR)DSS, VDS= 80% V(BR)DSS
Table 3.
Symbol
Tl
Table 4.
Thermal data
Parameter
Maximum lead temperature for soldering
purpose
Avalanche characteristics
Symbol
Parameter
Value
Unit
IAR
Avalanche current, repetitive or not-repetitive
(pulse width limited by Tj max)
2
A
EAS
Single pulse avalanche energy
(starting Tj = 25°C, ID = IAR, VDD = 50 V)
140
mJ
Doc ID 022505 Rev 2
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Electrical characteristics
2
STF8NM50N
Electrical characteristics
(TC = 25 °C unless otherwise specified)
Table 5.
Symbol
V(BR)DSS
On /off states
Parameter
Test conditions
Drain-source
breakdown voltage
(VGS = 0)
ID = 1 mA
Min.
Typ.
Max.
Unit
500
V
IDSS
VDS = 500 V
Zero gate voltage
drain current (VGS = 0) VDS = 500 V, TC = 125 °C
1
100
µA
µA
IGSS
Gate-body leakage
current (VDS = 0)
±100
nA
3
4
V
0.73
0.79
Ω
Min.
Typ.
Max.
Unit
VDS = 50 V, f = 1 MHz,
VGS = 0
-
364
33
1.2
-
pF
pF
pF
VDS = 0 to 50 V, VGS = 0
-
147.5
-
pF
VGS = ± 25 V
VGS(th)
Gate threshold voltage VDS = VGS, ID = 250 µA
RDS(on)
Static drain-source on
resistance
Table 6.
Symbol
Ciss
Coss
Crss
2
VGS = 10 V, ID = 2.5 A
Dynamic
Parameter
Test conditions
Input capacitance
Output capacitance
Reverse transfer
capacitance
Equivalent output
Coss(eq)(1) capacitance time
related
RG
Intrinsic gate
resistance
f = 1 MHz open drain
-
5.4
-
Ω
Qg
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain charge
VDD = 400 V, ID = 5 A,
VGS = 10 V
(see Figure 14)
-
14
3
7
-
nC
nC
nC
1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS
increases from 0 to 80% VDSS
Table 7.
Symbol
td(on)
tr
td(off)
tf
4/12
Switching times
Parameter
Turn-on delay time
Rise time
Turn-off-delay time
Fall time
Test conditions
VDD = 250 V, ID = 5 A,
RG = 4.7 Ω, VGS = 10 V
(see Figure 13)
Doc ID 022505 Rev 2
Min.
Typ.
-
7
4.4
25
8.8
Max
Unit
-
ns
ns
ns
ns
STF8NM50N
Electrical characteristics
Table 8.
Source drain diode
Symbol
Parameter
ISD
ISDM (1)
Source-drain current
Source-drain current (pulsed)
VSD (2)
Forward on voltage
trr
Qrr
IRRM
trr
Qrr
IRRM
Test conditions
Min.
Typ.
Max. Unit
-
5
20
A
A
ISD = 5 A, VGS = 0
-
1.5
V
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD = 5 A, di/dt = 100 A/µs
VDD = 60 V (see Figure 18)
-
187
1.3
14
ns
µC
A
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD = 5 A, di/dt = 100 A/µs
VDD = 60 V, Tj = 150 °C
(see Figure 18)
-
224
1.5
13
ns
µC
A
1. Pulse width limited by safe operating area.
2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%
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Electrical characteristics
STF8NM50N
2.1
Electrical characteristics (curves)
Figure 2.
Safe operating area
Figure 3.
Thermal impedance
Figure 5.
Transfer characteristics
AM07917v1
ID
(A)
)
on
10µs
D
S(
O
Li per
m at
ite io
d ni
by n
m this
ax a
R rea
is
10
1
100µs
1ms
10ms
Tj=150°C
Tc=25°C
0.1
Sinlge
pulse
0.01
0.1
Figure 4.
10
1
100
VDS(V)
Output characteristics
AM07917v1
ID
(A)
VGS=10V
10
AM07918v1
ID
(A)
VDS= 20 V
10
7V
8
8
6V
6
6
4
4
5V
2
2
0
0
Figure 6.
20
10
30
Static drain-source on resistance
AM07919v1
RDS(on)
(Ω)
0.77
0
0
VDS(V)
Figure 7.
2
4
AM03195v1
VDD=400 V
12
400
ID=5 A
350
VDS
10
0.76
VGS(V)
Gate charge vs gate-source voltage
VGS
(V)
VGS=10V
8
6
300
0.75
8
250
6
200
0.74
0.73
150
0.72
4
100
0.71
2
0.7
0.69
0
6/12
1
2
3
4
5 ID(A)
Doc ID 022505 Rev 2
50
0
0
5
10
15
0
Qg(nC)
STF8NM50N
Figure 8.
Electrical characteristics
Capacitance variations
Figure 9.
AM07921v1
C
(pF)
Output capacitance stored energy
AM07922v1
E
(µJ)
1000
Ciss
2
100
Coss
1
10
Crss
1
0
1
10
100
Figure 10. Normalized gate threshold voltage
vs temperature
AM07923v1
VGS(th)
(norm)
0
0
VDS(V)
ID = 250 µA
1.3
0.80
0.9
50
75 100
500 VDS(V)
AM07924v1
ID = 2.5 A
0.90
25
400
RDS(on)
(norm)
2.1
1.7
0
300
Figure 11. Normalized on resistance vs
temperature
1.00
0.70
-50 -25
200
100
TJ(°C)
0.5
-50 -25
0
25
50
75 100
TJ(°C)
Figure 12. Normalized VDS vs temperature
AM09028v1
VDS
(norm)
ID=1mA
1.10
1.08
1.06
1.04
1.02
1.00
0.98
0.96
0.94
0.92
-50 -25
0
25
50
75 100
TJ(°C)
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Test circuits
3
STF8NM50N
Test circuits
Figure 13. Switching times test circuit for
resistive load
Figure 14. Gate charge test circuit
VDD
12V
47kΩ
1kΩ
100nF
3.3
µF
2200
RL
µF
VGS
IG=CONST
VDD
100Ω
Vi=20V=VGMAX
VD
RG
2200
µF
D.U.T.
D.U.T.
VG
2.7kΩ
PW
47kΩ
1kΩ
PW
AM01468v1
AM01469v1
Figure 15. Test circuit for inductive load
Figure 16. Unclamped inductive load test
switching and diode recovery times
circuit
A
A
D.U.T.
FAST
DIODE
B
B
L
A
D
G
VD
L=100µH
S
3.3
µF
B
25 Ω
1000
µF
D
VDD
2200
µF
3.3
µF
VDD
ID
G
RG
S
Vi
D.U.T.
Pw
AM01470v1
Figure 17. Unclamped inductive waveform
AM01471v1
Figure 18. Switching time waveform
ton
V(BR)DSS
tdon
VD
toff
tr
tdoff
tf
90%
90%
IDM
10%
ID
VDD
10%
0
VDD
VDS
90%
VGS
AM01472v1
8/12
0
10%
Doc ID 022505 Rev 2
AM01473v1
STF8NM50N
4
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com. ECOPACK
is an ST trademark.
Doc ID 022505 Rev 2
9/12
Package mechanical data
Table 9.
STF8NM50N
TO-220FP mechanical data
mm
Dim.
Min.
Typ.
Max.
A
4.4
4.6
B
2.5
2.7
D
2.5
2.75
E
0.45
0.7
F
0.75
1
F1
1.15
1.70
F2
1.15
1.70
G
4.95
5.2
G1
2.4
2.7
H
10
10.4
L2
16
L3
28.6
30.6
L4
9.8
10.6
L5
2.9
3.6
L6
15.9
16.4
L7
9
9.3
Dia
3
3.2
Figure 19. TO-220FP drawing
L7
E
A
B
D
Dia
L5
L6
F1
F2
F
G
H
G1
L4
L2
L3
7012510_Rev_K
10/12
Doc ID 022505 Rev 2
STF8NM50N
5
Revision history
Revision history
Table 10.
Document revision history
Date
Revision
Changes
17-Nov-2011
1
First release.
18-Nov-2011
2
Updated dv/dt in Table 2: Absolute maximum ratings.
Doc ID 022505 Rev 2
11/12
STF8NM50N
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