STF9N80K5,
STFI9N80K5
N-channel 800 V, 0.73 Ω typ., 7 A MDmesh™ K5
Power MOSFETs in TO-220FP and I²PAKFP packages
Datasheet - production data
Features
Order code
STF9N80K5
STFI9N80K5
TO-220FP
I2PAKFP (TO-281)
Figure 1: Internal schematic diagram
D(2)
VDS
RDS(on) max.
ID
800 V
0.90 Ω
7A
Industry’s lowest RDS(on) x area
Industry’s best figure of merit (FoM)
Ultra-low gate charge
100% avalanche tested
Zener-protected
Applications
Switching applications
Description
G(1)
S(3)
AM15572v1_no_tab
This very high voltage N-channel Power
MOSFET is designed using MDmesh™ K5
technology based on an innovative proprietary
vertical structure. The result is a dramatic
reduction in on-resistance and ultra-low gate
charge for applications requiring superior power
density and high efficiency.
Table 1: Device summary
Order code
STF9N80K5
STFI9N80K5
November 2015
Marking
Package
TO-220FP
9N80K5
I²PAKFP(TO-281)
DocID028359 Rev 2
This is information on a product in full production.
Packing
Tube
1/16
www.st.com
Contents
STF9N80K5, STFI9N80K5
Contents
1
Electrical ratings ............................................................................. 3
2
Electrical characteristics ................................................................ 4
2.1
Electrical characteristics (curves) ...................................................... 6
3
Test circuits ..................................................................................... 9
4
Package information ..................................................................... 10
5
2/16
4.1
TO-220FP package information ...................................................... 11
4.2
I2PAKFP (TO-281) package information ......................................... 13
Revision history ............................................................................ 15
DocID028359 Rev 2
STF9N80K5, STFI9N80K5
1
Electrical ratings
Electrical ratings
Table 2: Absolute maximum ratings
Symbol
VGS
Parameter
Value
Unit
± 30
V
ID
Gate-source voltage
Drain current (continuous) at TC = 25 °C
7
A
(1)
ID
Drain current (continuous) at TC = 100 °C
4.4
A
(2)
ID
Drain current (pulsed)
28
A
PTOT
Total dissipation at TC = 25 °C
25
W
VISO
Insulation withstand voltage (RMS) from all three leads to external
heat sink (t=1 s; TC=25 °C)
2500
V
(1)
dv/dt
(3)
Peak diode recovery voltage slope
4.5
dv/dt
(4)
MOSFET dv/dt ruggedness
50
Tstg
Storage temperature
TJ
Operating junction temperature
V/ns
- 55 to 150
°C
Notes:
(1)
(2)
Limited by maximum junction temperature.
Pulse width limited by safe operating area
(3)
ISD ≤ 7 A, di/dt 100 A/μs; VDS peak < V(BR)DSS,VDD= 640 V
(4)
VDS ≤ 640 V
Table 3: Thermal data
Symbol
Parameter
Rthj-case
Thermal resistance junction-case
Rthj-amb
Thermal resistance junction-ambient
Value
Unit
5
°C/W
62.5
°C/W
Table 4: Avalanche characteristics
Symbol
Parameter
Value
Unit
IAR
Avalanche current, repetitive or not repetitive (pulse width limited by T jmax)
2.4
A
EAR
Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V)
200
mJ
DocID028359 Rev 2
3/16
Electrical characteristics
2
STF9N80K5, STFI9N80K5
Electrical characteristics
TC = 25 °C unless otherwise specified
Table 5: On/off-state
Symbol
V(BR)DSS
Parameter
Drain-source breakdown voltage
Test conditions
Min.
VGS = 0 V, ID = 1 mA
800
Typ.
Max.
Unit
V
VGS = 0 V, VDS = 800 V
1
µA
IDSS
Zero gate voltage drain current
VGS = 0 V, VDS = 800 V
TC = 125 °C
50
µA
IGSS
Gate body leakage current
VDS = 0 V, VGS = ±20 V
±10
µA
VGS(th)
Gate threshold voltage
VDS = VGS, ID = 100 µA
4
5
V
RDS(on)
Static drain-source on-resistance
VGS = 10 V, ID = 3.5 A
0.73
0.90
Ω
Min.
Typ.
Max.
Unit
-
340
-
pF
-
37
-
pF
-
0.65
-
pF
-
61
-
pF
-
22
-
pF
3
Table 6: Dynamic
Symbol
Ciss
Parameter
Test conditions
Input capacitance
VDS = 100 V, f = 1 MHz,
VGS = 0 V
Coss
Output capacitance
Crss
Reverse transfer capacitance
(1)
Co(tr)
(2)
Co(er)
Equivalent capacitance time
related
Equivalent capacitance energy
related
VDS = 0 to 640 V,
VGS = 0 V
Rg
Intrinsic gate resistance
f = 1 MHz , ID= 0 A
-
7
-
Ω
Qg
Total gate charge
-
12
-
nC
Qgs
Gate-source charge
Qgd
Gate-drain charge
VDD = 640 V, ID = 7 A
VGS= 10 V
See (Figure 16: "Test
circuit for gate charge
behavior")
-
3.8
-
nC
-
6.7
-
nC
Notes:
(1)
Time related is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS
increases from 0 to 80% VDSS
(2)
Energy related is defined as a constant equivalent capacitance giving the same stored energy as C oss when VDS
increases from 0 to 80% VDSS
Table 7: Switching times
Symbol
td(on)
tr
td(off)
tf
4/16
Parameter
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Test conditions
VDD= 400 V, ID =3.5 A,
RG = 4.7 Ω, VGS = 10 V
See (Figure 15: "Test circuit for
resistive load switching times"
and Figure 20: "Switching time
waveform")
DocID028359 Rev 2
Min.
Typ.
Max.
Unit
-
11
-
ns
-
5.7
-
ns
-
65.3
-
ns
-
13.6
-
ns
STF9N80K5, STFI9N80K5
Electrical characteristics
Table 8: Source-drain diode
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Source-drain current
-
7
A
(1)
ISDM
Source-drain current (pulsed)
-
28
A
(2)
VSD
Forward on voltage
ISD = 7 A, VGS = 0 V
-
1.5
V
Trr
Reverse recovery time
-
292
ns
Qrr
Reverrse recovery charge
-
2.66
µC
IRRM
Reverse recovery current
ISD = 7 A, di/dt = 100 A/µs,
VDD = 60 V
See Figure 17: "Test circuit
for inductive load switching
and diode recovery times"
-
18.2
A
ISD = 7 A, di/dt = 100 A/µs
VDD = 60 V, Tj = 150 °C
See Figure 17: "Test circuit
for inductive load switching
and diode recovery times"
-
477
ns
-
3.91
µC
-
16.4
A
ISD
Trr
Reverse recovery time
Qrr
Reverse recovery charge
IRRM
Reverse recovery current
Notes:
(1)
(2)
Pulse width limited by safe operating area
Pulsed: pulse duration = 300 µs, duty cycle 1.5%
Table 9: Gate-source Zener diode
Symbol
V(BR)GSO
Parameter
Gate-source breakdown voltage
Test conditions
IGS= ± 1mA, ID= 0 A
Min.
Typ.
Max.
Unit
30
-
-
V
The built-in back-to-back Zener diodes are specifically designed to enhance the ESD
performance of the device. The Zener voltage facilitates efficient and cost-effective device
integrity protection,thus eliminating the need for additional external componentry.
DocID028359 Rev 2
5/16
Electrical characteristics
2.2
STF9N80K5, STFI9N80K5
Electrical characteristics (curves)
Figure 2: Safe operating area
Figure 3: Thermal impedance
K
GC20940_ZTH
δ=0.5
0.1
δ=0.2
0.05
0.02
10 -1
0.01
Single pulse
10 -2
10
6/16
-3
10-4
10-3
10
-2
10
-1
10
0
tp(s)
Figure 4: Output characteristics
Figure 5: Transfer characteristics
Figure 6: Gate charge vs gate-source voltage
Figure 7: Static drain-source on-resistance
DocID028359 Rev 2
STF9N80K5, STFI9N80K5
Electrical characteristics
Figure 8: Capacitance variations
Figure 9: Normalized gate threshold voltage
vs temperature
Figure 10: Normalized on-resistance vs
temperature
Figure 11: Normalized V(BR)DSS vs temperature
Figure 12: Output capacitance stored energy
Figure 13: Source-drain diode forward
characteristics
DocID028359 Rev 2
7/16
Electrical characteristics
STF9N80K5, STFI9N80K5
Figure 14: Maximum avalanche energy vs starting TJ
8/16
DocID028359 Rev 2
STF9N80K5, STFI9N80K5
3
Test circuits
Test circuits
Figure 15: Test circuit for resistive load
switching times
Figure 16: Test circuit for gate charge
behavior
Figure 17: Test circuit for inductive load
switching and diode recovery times
Figure 18: Unclamped inductive load test
circuit
Figure 19: Unclamped inductive waveform
Figure 20: Switching time waveform
DocID028359 Rev 2
9/16
Package information
4
STF9N80K5, STFI9N80K5
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
10/16
DocID028359 Rev 2
STF9N80K5, STFI9N80K5
4.1
Package information
TO-220FP package information
Figure 21: TO-220FP package outline
DocID028359 Rev 2
11/16
Package information
STF9N80K5, STFI9N80K5
Table 10: TO-220FP package mechanical data
mm
Dim.
Min.
Max.
A
4.4
4.6
B
2.5
2.7
D
2.5
2.75
E
0.45
0.7
F
0.75
1
F1
1.15
1.70
F2
1.15
1.70
G
4.95
5.2
G1
2.4
2.7
H
10
10.4
L2
12/16
Typ.
16
L3
28.6
30.6
L4
9.8
10.6
L5
2.9
3.6
L6
15.9
16.4
L7
9
9.3
Dia
3
3.2
DocID028359 Rev 2
STF9N80K5, STFI9N80K5
4.2
Package information
2
I PAKFP (TO-281) package information
Figure 22: I²PAKFP (TO-281) package outline
8291506 Re v. C
DocID028359 Rev 2
13/16
Package information
STF9N80K5, STFI9N80K5
Table 11: I²PAKFP (TO-281) mechanical data
mm
Dim.
Min.
Typ.
A
4.40
4.60
B
2.50
2.70
D
2.50
2.75
D1
0.65
0.85
E
0.45
0.70
F
0.75
1.00
F1
14/16
Max.
1.20
G
4.95
5.20
H
10.00
10.40
L1
21.00
23.00
L2
13.20
14.10
L3
10.55
10.85
L4
2.70
3.20
L5
0.85
L6
7.50
DocID028359 Rev 2
1.25
7.60
7.70
STF9N80K5, STFI9N80K5
5
Revision history
Revision history
Table 12: Document revision history
Date
Revision
06-Oct-2015
1
First release.
2
Modified: Table 2: "Absolute maximum ratings", Table 3: "Thermal
data", Table 4: "Avalanche characteristics", Table 6: "Dynamic", Table
7: "Switching times" and Table 8: "Source-drain diode".
Added: Section 3.1: "Electrical characteristics (curves)"
Minor text changes
11-Nov-2015
Changes
DocID028359 Rev 2
15/16
STF9N80K5, STFI9N80K5
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST
products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the
design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2015 STMicroelectronics – All rights reserved
16/16
DocID028359 Rev 2