STFH13N60M2

STFH13N60M2 N-channel 600 V, 0.35 Ω typ., 11 A MDmesh™ M2 Power MOSFET in a TO-220FP wide creepage package Datasheet - production data Features      Order code VDS RDS(on) max ID STFH13N60M2 600 V 0.38 Ω 11 A Extremely low gate charge Excellent output capacitance (COSS) profile 100% avalanche tested Zener-protected Wide creepage distance of 4.25 mm between the pins Applications  Switching applications Description Figure 1: Internal schematic diagram D(2) This device is an N-channel Power MOSFET developed using MDmesh™ M2 technology. Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance and optimized switching characteristics, rendering it suitable for the most demanding high efficiency converters. The TO-220FP wide creepage package provides increased surface insulation for Power MOSFETs to prevent failure due to arcing, which can occur in polluted environments. G(1) S(3) AM15572v1_no_tab Table 1: Device summary Order code Marking Package Packaging STFH13N60M2 13N60M2 TO-220FP wide creepage Tube June 2016 DocID029304 Rev 2 This is information on a product in full production. 1/12 www.st.com Contents STFH13N60M2 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package mechanical data ............................................................... 9 4.1 5 2/12 TO-220FP wide creepage package information ................................ 9 Revision history ............................................................................ 11 DocID029304 Rev 2 STFH13N60M2 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter VGS ID Value Unit Gate-source voltage ± 25 V Drain current (continuous) at TC = 25 °C 11(1) A (1) A Drain current (continuous) at TC = 100 °C 7 IDM(2) Drain current (pulsed) 44 A PTOT Total dissipation at TC = 25 °C 25 W VISO Insulation withstand voltage (RMS) from all three leads to external heat sink (t = 1 s; TC = 25 °C) 2500 V ID dv/dt (3) Peak diode recovery voltage slope 15 dv/dt (4) MOSFET dv/dt ruggedness 50 Tstg Storage temperature range Tj Operating junction temperature range V/ns - 55 to 150 °C Notes: (1)Limited (2)Pulse (3)I SD (4)V by maximum junction temperature. width limited by safe operating area. ≤ 11 A, di/dt ≤ 400 A/µs; VDS(peak < V(BR)DSS, VDD = 400 V DS ≤ 480 V Table 3: Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case max Rthj-amb Thermal resistance junction-ambient max Value Unit 5 °C/W 62.5 °C/W Table 4: Avalanche characteristics Symbol Parameter Value Unit IAR Avalanche current, repetitive or not repetitive (pulse width limited by T jmax) 2.8 A EAS Single pulse avalanche energy (starting Tj = 25°C, ID = IAR; VDD = 50 V) 125 mJ DocID029304 Rev 2 3/12 Electrical characteristics 2 STFH13N60M2 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 5: On /off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage ID = 1 mA, VGS = 0 V Min. Typ. Max. 600 Unit V 1 µA VDS = 600 V, , VGS = 0 V, TC = 125 °C(1) 100 µA Gate-body leakage current VGS = ± 25 V, VDS = 0 V ±10 µA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 3 4 V RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 5.5 A 0.35 0.38 Ω Min. Typ. Max. Unit - 580 - pF - 32 - pF - 1.1 - pF IDSS Zero gate voltage drain current IGSS VDS = 600 V, VGS = 0 V 2 Notes: (1)Defined by design, not subject to production test. Table 6: Dynamic Symbol Parameter Test conditions Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance C (1) oss eq. Equivalent output capacitance VDS = 0 to 480 V, VGS = 0 V - 120 - pF RG Intrinsic gate resistance f = 1 MHz open drain - 6.6 - Ω Qg Total gate charge - 17 - nC Qgs Gate-source charge - 2.5 - nC Qgd Gate-drain charge - 9 - nC VDS = 100 V, f = 1 MHz, VGS = 0 V VDD = 480 V, ID = 11 A, VGS = 10 V (see Figure 15: "Test circuit for gate charge behavior" ) Notes: (1)C oss eq. is defined as a constant equivalent capacitance giving the same charging time as C oss when VDS increases from 0 to 80% VDSS. Table 7: Switching times Symbol td(on) tr td(off) tf 4/12 Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions Min. Typ. Max. Unit VDD = 300 V, ID = 5.5 A, RG = 4.7 Ω, VGS = 10 V ( see Figure 14: "Test circuit for resistive load switching times" and Figure 19: "Switching time waveform" ) - 11 - ns - 10 - ns - 41 - ns - 9.5 - ns DocID029304 Rev 2 STFH13N60M2 Electrical characteristics Table 8: Source drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit ISD Source-drain current - 11 A ISDM(1) Source-drain current (pulsed) - 44 A VSD(2) Forward on voltage - 1.6 V trr ISD = 11 A, VGS = 0 V Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ISD = 11 A, di/dt = 100 A/µs, VDD = 60 V ( see Figure 16: "Test circuit for inductive load switching and diode recovery times" ) trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ISD = 11 A, di/dt = 100 A/µs, VDD = 60 V, Tj = 150 °C, (see Figure 16: "Test circuit for inductive load switching and diode recovery times" ) - 297 ns - 2.8 µC - 18.5 A - 394 ns - 3.8 µC - 19 A Notes: (1)Pulse width limited by safe operating area. (2)Pulsed: pulse duration = 300 µs, duty cycle 1.5%. DocID029304 Rev 2 5/12 Electrical characteristics 2.1 STFH13N60M2 Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Normalized V(BR)DSS vs temperature Figure 7: Static drain-source on-resistance W 6/12 DocID029304 Rev 2 STFH13N60M2 Electrical characteristics Figure 8: Gate charge vs gate-source voltage V GS (V) 10 V DS (V) V DD=480V ID=11A V DS 500 Figure 9: Capacitance variations AM15717v1 C (pF) 1000 Ciss 400 8 100 300 6 Coss 10 4 200 2 100 0 0 4 8 12 16 0 Q g(nC) Figure 10: Normalized gate threshold voltage vs temperature 1 Crss 0.1 0.1 1 10 100 V DS(V) Figure 11: Normalized on-resistance vs temperature ID=17 A Figure 12: Source-drain diode forward characteristics Figure 13: Output capacitance stored energy AM15721v1 Eoss (µJ) 4 3 2 1 0 0 DocID029304 Rev 2 100 200 300 400 500 V DS(V) 7/12 Test circuits 3 STFH13N60M2 Test circuits Figure 15: Test circuit for gate charge behavior Figure 14: Test circuit for resistive load switching times Figure 16: Test circuit for inductive load switching and diode recovery times Figure 17: Unclamped inductive load test circuit Figure 18: Unclamped inductive waveform 8/12 DocID029304 Rev 2 Figure 19: Switching time waveform STFH13N60M2 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 4.1 TO-220FP wide creepage package information Figure 20: TO-220FP wide creepage package outline DM00260252_1 DocID029304 Rev 2 9/12 Package mechanical data STFH13N60M2 Table 9: TO-220FP wide creepage package mechanical data mm Dim. 10/12 Min. Typ. Max. A 4.60 4.70 4.80 B 2.50 2.60 2.70 D 2.49 2.59 2.69 E 0.46 0.59 F 0.76 0.89 F1 0.96 1.25 F2 1.11 1.40 G 8.40 8.50 8.60 G1 4.15 4.25 4.35 H 10.90 11.00 11.10 L2 15.25 15.40 15.55 L3 28.70 29.00 29.30 L4 10.00 10.20 10.40 L5 2.55 2.70 2.85 L6 16.00 16.10 16.20 L7 9.05 9.15 9.25 Dia 3.00 3.10 3.20 DocID029304 Rev 2 STFH13N60M2 5 Revision history Revision history Table 10: Document revision history Date Revision Changes 12-May-2016 1 Initial release 10-Jun-2016 2 Document status promoted from preliminary to production data. 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All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved 12/12 DocID029304 Rev 2