STFH24N60M2

STFH24N60M2 N-channel 600 V, 0.168 Ω typ., 18 A MDmesh™ M2 Power MOSFET in a TO-220FP wide creepage package Datasheet - production data Features Order code VDS @ TJmax RDS(on) max ID STFH24N60M2 650 V 0.19 Ω 18 A      Extremely low gate charge Excellent output capacitance (COSS) profile 100% avalanche tested Zener-protected Wide creepage distance of 4.25 mm between the pins Applications   Figure 1: Internal schematic diagram D(2) G(1) Switching applications LLC converters, resonant converters Description This device is an N-channel Power MOSFET developed using MDmesh™ M2 technology. Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance and optimized switching characteristics, rendering it suitable for the most demanding high efficiency converters. The TO-220FP wide creepage package provides increased surface insulation for Power MOSFETs to prevent failure due to arcing, which can occur in polluted environments. S(3) AM15572v1_no_tab Table 1: Device summary Order code Marking Package Packing STFH24N60M2 24N60M2 TO-220FP wide creepage Tube June 2016 DocID029415 Rev 2 This is information on a product in full production. 1/12 www.st.com Contents STFH24N60M2 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package information ....................................................................... 9 4.1 5 2/12 TO-220FP wide creepage package information ................................ 9 Revision history ............................................................................ 11 DocID029415 Rev 2 STFH24N60M2 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol VGS ID ID IDM (2) Parameter Value Unit Gate-source voltage ± 25 V Drain current (continuous) at TC = 25 °C 18 (1) A Drain current (continuous) at TC = 100 °C 12 (1) A (1) A 72 Drain current (pulsed) PTOT Total dissipation at TC = 25 °C 30 W dv/dt (3) Peak diode recovery voltage slope 15 V/ns dv/dt (4) MOSFET dv/dt ruggedness 50 V/ns 2500 V - 55 to 150 °C VISO Insulation withstand voltage (RMS) from all three leads to external heat sink (t = 1 s; TC = 25 °C) Tstg Storage temperature range Tj Operating junction temperature range Notes: (1)Limited (2)Pulse (3)I SD (4)V by maximum junction temperature. width limited by safe operating area. ≤ 18 A, di/dt ≤ 400 A/µs; VDSpeak < V(BR)DSS, VDD = 400 V. DS ≤ 480 V. Table 3: Thermal data Symbol Parameter Value Unit Rthj-case Thermal resistance junction-case max 4.2 °C/W Rthj-amb Thermal resistance junction-ambient max 62.5 °C/W Table 4: Avalanche characteristics Symbol Parameter Value Unit IAR Avalanche current, repetitive or not repetitive (pulse width limited by T jmax) 3.5 A EAS Single pulse avalanche energy (starting Tj=25 °C, ID= IAR; VDD=50 V) 180 mJ DocID029415 Rev 2 3/12 Electrical characteristics 2 STFH24N60M2 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 5: On /off states Symbol Parameter Test conditions V(BR)DSS Drain-source breakdown voltage VGS = 0, ID = 1 mA Min. Typ. Max. 600 Unit V VGS = 0, VDS = 600 V 1 µA VGS = 0, VDS = 600 V, TC=125 °C(1) 100 µA ±10 µA 3 4 V 0.168 0.190 Ω Min. Typ. Max. Unit - 1060 - pF - 55 - pF - 2.2 - pF IDSS Zero gate voltage drain current IGSS Gate-body leakage current VDS = 0, VGS = ± 25 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source on- resistance VGS = 10 V, ID = 9 A 2 Notes: (1)Defined by design, not subject to production test. Table 6: Dynamic Symbol Parameter Test conditions Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Coss eq.(1) Equivalent output capacitance VDS= 0 to 480 V, VGS= 0 V - 258 - pF RG Intrinsic gate resistance f = 1 MHz, ID=0 A - 7 - Ω Qg Total gate charge - 29 - nC Qgs Gate-source charge - 6 - nC Qgd Gate-drain charge VDD = 480 V, ID = 18 A, VGS = 10 V (see Figure 15: "Test circuit for gate charge behavior") - 12 - nC VDS = 100 V, f = 1 MHz, VGS = 0 V Notes: (1) 4/12 Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases DocID029415 Rev 2 from 0 to 80% VDSS. STFH24N60M2 Electrical characteristics Table 7: Switching times Symbol Parameter td(on) Turn-on delay time tr Rise time td(off) Turn-off delay time tf Fall time Test conditions VDD = 300 V, ID = 9 A, RG = 4.7 Ω, VGS = 10 V (see Figure 14: "Test circuit for resistive load switching times" and Figure 19: "Switching time waveform") Min. Typ. Max. Unit - 14 - ns - 9 - ns - 60 - ns - 15 - ns Min. Typ. Max. Unit Table 8: Source drain diode Symbol ISD(1) ISDM(1)(2) VSD(3) Parameter Source-drain current - 18 A Source-drain current (pulsed) - 72 A - 1.6 V Forward on voltage Reverse recovery time trr Test conditions Qrr Reverse recovery charge IRRM Reverse recovery current trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ISD = 18 A, VGS = 0 V ISD = 18 A, di/dt = 100 A/µs VDD = 60 V (see Figure 16: "Test circuit for inductive load switching and diode recovery times") ISD = 18 A, di/dt = 100 A/µs VDD = 60 V, Tj = 150 °C (see Figure 16: "Test circuit for inductive load switching and diode recovery times") - 332 ns - 4 µC - 24 A - 450 ns - 5.5 µC - 25 A Notes: (1)The value is rated according to Rthj-case and limited by package. (2)Pulse width limited by safe operating area (3)Pulsed: pulse duration = 300 µs, duty cycle 1.5% DocID029415 Rev 2 5/12 Electrical characteristics 2.1 STFH24N60M2 Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance 6/12 DocID029415 Rev 2 STFH24N60M2 Electrical characteristics Figure 8: Capacitance variations Figure 9: Output capacitance stored energy Figure 10: Normalized gate threshold voltage vs temperature Figure 11: Normalized on-resistance vs temperature Figure 12: Source-drain diode forward characteristics Figure 13: Normalized V(BR)DSS vs temperature DocID029415 Rev 2 7/12 Test circuits 3 STFH24N60M2 Test circuits Figure 15: Test circuit for gate charge behavior Figure 14: Test circuit for resistive load switching times Figure 16: Test circuit for inductive load switching and diode recovery times Figure 17: Unclamped inductive load test circuit Figure 18: Unclamped inductive waveform 8/12 DocID029415 Rev 2 Figure 19: Switching time waveform STFH24N60M2 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 4.1 TO-220FP wide creepage package information Figure 20: TO-220FP wide creepage package outline DM00260252_1 DocID029415 Rev 2 9/12 Package information STFH24N60M2 Table 9: TO-220FP wide creepage package mechanical data mm Dim. 10/12 Min. Typ. Max. A 4.60 4.70 4.80 B 2.50 2.60 2.70 D 2.49 2.59 2.69 E 0.46 0.59 F 0.76 0.89 F1 0.96 1.25 F2 1.11 1.40 G 8.40 8.50 8.60 G1 4.15 4.25 4.35 H 10.90 11.00 11.10 L2 15.25 15.40 15.55 L3 28.70 29.00 29.30 L4 10.00 10.20 10.40 L5 2.55 2.70 2.85 L6 16.00 16.10 16.20 L7 9.05 9.15 9.25 Dia 3.00 3.10 3.20 DocID029415 Rev 2 STFH24N60M2 5 Revision history Revision history Table 10: Document revision history Date Revision Changes 07-Jun-2016 1 First release. 16-Jun-2016 2 Document status promoted from preliminary data to production data. Minor text changes. DocID029415 Rev 2 11/12 STFH24N60M2 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved 12/12 DocID029415 Rev 2