STFI12N60M2

STFI12N60M2 N-channel 600 V, 0.395 Ω typ., 9 A MDmesh™ M2 Power MOSFET in an I²PAKFP package Datasheet - production data Features Order code VDS RDS(on) max. ID PTOT STFI12N60M2 600 V 0.450 Ω 9A 25 W • • • • Extremely low gate charge Excellent output capacitance (COSS) profile 100% avalanche tested Zener-protected Applications • Figure 1: Internal schematic diagram D(2) Switching applications Description This device is an N-channel Power MOSFET developed using MDmesh™ M2 technology. Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance and optimized switching characteristics, rendering it suitable for the most demanding high efficiency converters. G(1) S(3) AM15572v1_no_tab Table 1: Device summary Order code Marking Package Packing STFI12N60M2 12N60M2 I²PAKFP Tube May 2015 DocID027899 Rev 1 This is information on a product in full production. 1/12 www.st.com Contents STFI12N60M2 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package information ....................................................................... 9 4.1 5 2/12 I²PAKFP (TO-281) package information ........................................... 9 Revision history ............................................................................ 11 DocID027899 Rev 1 STFI12N60M2 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol VGS (1) ID (2) IDM PTOT Parameter Gate-source voltage Value Unit ±25 V Drain current (continuous) at Tcase = 25 °C 9 Drain current (continuous) at Tcase = 100 °C 5.7 Drain current (pulsed) 36 A W A Total dissipation at Tcase = 25 °C 25 dv/dt (3) Peak diode recovery voltage slope 15 dv/dt (4) MOSFET dv/dt ruggedness 50 VISO Insulation withstand voltage (RMS) from all three leads to external heat sink (t = 1 s; TC = 25 °C) 2.5 kV Tstg Storage temperature -55 to 150 °C Value Unit Tj Operating junction temperature V/ns Notes: (1) (2) Limited by maximum junction temperature. Pulse width is limited by safe operating area. (3) ISD ≤ 9 A, di/dt=400 A/μs; VDS(peak) < V(BR)DSS, VDD = 80% V(BR)DSS. (4) VDS ≤ 480 V. Table 3: Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case Rthj-amb Thermal resistance junction-ambient 5 62.5 °C/W Table 4: Avalanche characteristics Symbol (1) IAR (2) EAR Parameter Value Unit Avalanche current, repetitive or not repetitive 2.6 A Single pulse avalanche energy 117 mJ Notes: (1) (2) Pulse width limited by Tjmax. starting Tj = 25 °C, ID = IAR, VDD = 50 V. DocID027899 Rev 1 3/12 Electrical characteristics 2 STFI12N60M2 Electrical characteristics (Tcase = 25 °C unless otherwise specified) Table 5: Static Symbol Parameter Test conditions V(BR)DSS Drain-source breakdown voltage VGS = 0 V, ID = 1 mA Min. Typ. Max. 600 Unit V VGS = 0 V, VDS = 600 V 1 VGS = 0 V, VDS = 600 V, Tcase = 125 °C 100 ±10 µA 3 4 V 0.395 0.450 Ω Min. Typ. Max. Unit - 538 - - 29 - - 1.1 - IDSS Zero gate voltage drain current IGSS Gate-body leakage current VDS = 0 V, VGS = ±25 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source onresistance VGS = 10 V, ID = 4.5 A 2 µA Table 6: Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Test conditions VDS = 100 V, f = 1 MHz, VGS = 0 V pF Equivalent output capacitance VDS = 0 to 480 V, VGS = 0 V - 106 - pF RG Intrinsic gate resistance f = 1 MHz, ID = 0 A - 7 - Ω Qg Total gate charge - 16 - Qgs Gate-source charge - 2.3 - Qgd Gate-drain charge VDD = 400 V, ID = 9 A, VGS = 10 V (see Figure 15: "Gate charge test circuit") - 8.5 - Coss eq. (1) nC Notes: (1) Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. Table 7: Switching times Symbol td(on) tr td(off) tf 4/12 Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions Min. Typ. Max. VDD = 300 V, ID = 4.5 A RG = 4.7 Ω, VGS = 10 V (see Figure 14: "Switching times test circuit for resistive load" and Figure 19: "Switching time waveform") - 9.2 - DocID027899 Rev 1 - 9.2 - - 56 - - 18 - Unit ns STFI12N60M2 Electrical characteristics Table 8: Source-drain diode Symbol ISD Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 9 A (1) Source-drain current (pulsed) - 36 A (2) Forward on voltage VGS = 0 V, ISD = 9 A - 1.6 V trr Reverse recovery time - 284 ns Qrr Reverse recovery charge - 2.4 µC IRRM Reverse recovery current ISD = 9 A, di/dt = 100 A/µs, VDD = 60 V (see Figure 16: "Test circuit for inductive load switching and diode recovery times") - 17 A - 404 ns - 3.5 µC - 17.5 A ISDM VSD trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ISD = 9 A, di/dt = 100 A/µs, VDD = 60 V, Tj = 150 °C (see Figure 16: "Test circuit for inductive load switching and diode recovery times") Notes: (1) (2) Pulse width is limited by safe operating area. Pulse test: pulse duration = 300 µs, duty cycle 1.5%. DocID027899 Rev 1 5/12 Electrical characteristics 2.1 6/12 STFI12N60M2 Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance DocID027899 Rev 1 STFI12N60M2 Electrical characteristics Figure 8: Capacitance variations Figure 9: Normalized gate threshold voltage vs temperature AM03184v1 VGS(th) (norm) 1.10 1.00 ID = 250 µA 0.90 0.80 0.70 -50 50 0 100 Tj(°C) Figure 10: Normalized on-resistance vs temperature Figure 11: Normalized V(BR)DSS vs temperature Figure 12: Output capacitance stored energy Figure 13: Source- drain diode forward characteristics VSD (V) GIPG290120151002ALS 1.1 Tj = -50 °C 1.0 Tj = -25 °C 0.9 Tj = 150 °C 0.8 0.7 0.6 0.5 DocID027899 Rev 1 0 4 8 12 16 ISD (A) 7/12 Test circuits 3 STFI12N60M2 Test circuits Figure 14: Switching times test circuit for resistive load Figure 15: Gate charge test circuit Figure 16: Test circuit for inductive load switching and diode recovery times Figure 17: Unclamped inductive load test circuit Figure 18: Unclamped inductive waveform Figure 19: Switching time waveform 8/12 DocID027899 Rev 1 STFI12N60M2 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK is an ST trademark. 4.1 I²PAKFP (TO-281) package information Figure 20: I²PAKFP (TO-281) package outline 8291506 Re v. C DocID027899 Rev 1 9/12 Package information STFI12N60M2 Table 9: I²PAKFP (TO-281) mechanical data mm Dim. Min. Typ. Max. A 4.40 - 4.60 B 2.50 2.70 D 2.50 2.75 D1 0.65 0.85 E 0.45 0.70 F 0.75 1.00 F1 10/12 1.20 G 4.95 5.20 H 10.00 10.40 L1 21.00 23.00 L2 13.20 14.10 L3 10.55 10.85 L4 2.70 3.20 L5 0.85 L6 7.50 DocID027899 Rev 1 1.25 7.60 7.70 STFI12N60M2 5 Revision history Revision history Table 10: Document revision history Date Revision 22-May-2015 1 DocID027899 Rev 1 Changes First release. 11/12 STFI12N60M2 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved 12/12 DocID027899 Rev 1