STFI13N80K5

STFI13N80K5 N-channel 800 V, 0.37 Ω typ.,12 A MDmesh™ K5 Power MOSFET in an I²PAKFP package Datasheet - production data Features Order code VDS STFI13N80K5 800 V RDS(on) ID PTOT 0.45 Ω 12 A 35 W • Fully insulated and low profile package with increased creepage path from pin to heatsink plate 1 2 • Industry’s lowest RDS(on) x area 3 • Industry’s best figure of merit (FoM) I2PAKFP • Ultra low gate charge • 100% avalanche tested Figure 1. Internal schematic diagram D(2) • Zener-protected Applications • Switching applications Description G(1) S(3) AM01476v1 This very high voltage N-channel Power MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in onresistance and ultra-low gate charge for applications requiring superior power density and high efficiency. Table 1. Device summary Order code Marking Package Packaging STFI13N80K5 13N80K5 I²PAKFP (TO-281) Tube December 2014 This is information on a product in full production. DocID027200 Rev 2 1/13 www.st.com 13 Contents STFI13N80K5 Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Test circuits 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2/13 .............................................. 9 DocID027200 Rev 2 STFI13N80K5 1 Electrical ratings Electrical ratings Table 2. Absolute maximum ratings Symbol Value Unit ± 30 V (1) A Drain current (continuous) at TC = 100 °C 7.6 (1) A IDM (2) Drain current (pulsed) 48(1) A PTOT Total dissipation at TC = 25 °C 35 W IAR Max current during repetitive or single pulse avalanche (pulse width limited by Tjmax) 4 A EAS Single pulse avalanche energy (starting TJ = 25 °C, ID=IAS, VDD= 50 V) 148 mJ Viso Insulation withstand voltage (RMS) from all three leads to external heat sink (t=1 s; TC=25 °C) 2500 V VGS ID ID Parameter Gate-source voltage Drain current (continuous) at TC = 25 °C 12 dv/dt (3) Peak diode recovery voltage slope 4.5 V/ns dv/dt(4) MOSFET dv/dt ruggedness 50 V/ns -55 to 150 °C Tj Tstg Operating junction temperature Storage temperature 1. Limited by package. 2. Pulse width limited by safe operating area. 3. ISD ≤ 12 A, di/dt ≤ 100 A/µs, VPeak ≤ V(BR)DSS 4. VDS ≤ 640 V Table 3. Thermal data Symbol Parameter Value Rthj-case Thermal resistance junction-case max 3.57 Rthj-amb Thermal resistance junction-amb max 62.5 Unit °C/W DocID027200 Rev 2 3/13 Electrical characteristics 2 STFI13N80K5 Electrical characteristics (TCASE = 25 °C unless otherwise specified). Table 4. On/off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage VGS= 0, ID = 1 mA Min. Typ. Max. 800 Unit V VGS = 0, VDS = 800 V 1 µA VGS = 0, VDS = 800 V, Tc=125 °C 50 µA ±10 µA 4 5 V 0.37 0.45 Ω Min. Typ. Max. Unit - 870 - pF - 50 - pF - 2 - pF - 110 - pF - 43 - pF IDSS Zero gate voltage drain current IGSS Gate body leakage current VDS = 0, VGS = ± 20 V VGS(th) Gate threshold voltage VDS = VGS, ID = 100 µA RDS(on) Static drain-source on-resistance VGS = 10 V, ID= 6 A 3 Table 5. Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Co(tr)(1) Test conditions VDS =100 V, f=1 MHz, VGS=0 Equivalent capacitance time related VGS = 0, VDS = 0 to 640 V Co(er)(2) Equivalent capacitance energy related RG Intrinsic gate resistance f = 1MHz, ID=0 - 5 - Ω Qg Total gate charge - 29 - nC Qgs Gate-source charge - 7 - nC Qgd Gate-drain charge VDD = 640 V, ID = 12 A VGS =10 V (see Figure 16) - 18 - nC 1. Time related is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS 2. Energy related is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS increases from 0 to 80% VDSS 4/13 DocID027200 Rev 2 STFI13N80K5 Electrical characteristics Table 6. Switching times Symbol td(on) tr Parameter Test conditions Turn-on delay time VDD = 400 V, ID = 6A, RG=4.7 Ω, VGS=10 V (see Figure 18) Rise time td(off) tf Turn-off delay time Fall time Min. Typ. Max. Unit - 16 - ns - 16 - ns - 42 - ns - 16 - ns Min. Typ. Max. Unit Table 7. Source drain diode Symbol ISD ISDM VSD 1. (1) Parameter Test conditions Source-drain current - 14 A Source-drain current (pulsed) - 56 A 1.5 V Forward on voltage VGS=0, ISD= 12 A - trr Reverse recovery time - 406 ns Qrr Reverse recovery charge - 5.7 µC IRRM Reverse recovery current ISD= 12 A, VDD= 60 V di/dt = 100 A/µs, (see Figure 17) - 28 A - 600 ns - 7.9 µC - 26 A Min. Typ. Max. Unit 30 - - V trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ISD= 12 A,VDD= 60 V di/dt=100 A/µs, Tj=150 °C (see Figure 17) Pulsed: pulse duration = 300 µs, duty cycle 1.5% Table 8. Gate-source Zener diode Symbol Parameter Test conditions V(BR)GSO Gate-source breakdown voltage IGS= ± 1mA, ID= 0 The built-in back-to-back Zener diodes have been specifically designed to enhance the ESD capability of the device. The Zener voltage is appropriate for efficient and cost-effective intervention to protect the device integrity. These integrated Zener diodes thus eliminate the need for external components. DocID027200 Rev 2 5/13 Electrical characteristics 2.1 STFI13N80K5 Electrical characteristics (curves) Figure 2. Safe operating area Figure 3. Thermal impedance AM15688v1 ID (A) 10 on ) 100µs S( Op Lim era ite tion d by in t m his ax ar RD ea is 10µs 1 1ms 10ms 0.1 Tj=150°C Tc=25°C Single pulse 0.01 0.1 10 1 100 VDS(V) Figure 4. Output characteristics Figure 5. Transfer characteristics AM15690v1 ID (A) VGS=11V 10V 30 AM15691v1 ID (A) VDS=20V 30 9V 25 25 20 20 8V 15 15 10 10 7V 5 5 6V 0 0 10 5 20 15 0 VDS(V) Figure 6. Normalized V(BR)DSS vs temperature AM15699v1 V(BR)DSS (norm) ID=1mA 4 5 6 9 8 7 10 VGS(V) Figure 7. Static drain-source on-resistance AM15693v1 RDS(on) (Ω) VGS=10V 1.1 0.6 1.05 1 0.4 0.95 0.2 0.9 0.85 -100 -50 6/13 0 50 100 150 TJ(°C) DocID027200 Rev 2 0 0 4 8 12 16 20 24 28 ID(A) STFI13N80K5 Electrical characteristics Figure 8. Gate charge vs gate-source voltage VGS (V) AM15692v1 VDS VDS (V) 600 12 VDD = 640V ID=12A 10 500 8 400 6 300 4 200 2 100 Figure 9. Capacitance variations AM15694v1 C (pF) 1000 Ciss 100 Coss 0 0 5 10 20 15 Crss 1 0.1 0 30 Qg(nC) 25 Figure 10. Normalized gate threshold voltage vs temperature AM15696v1 VGS(th) (norm) 10 1 10 100 VDS(V) Figure 11. Normalized on-resistance vs temperature AM15697v1 RDS(on) (norm) ID=100µA 1.2 ID=6A VGS=10V 2.5 1 2 0.8 1.5 0.6 1 0.4 0.5 0.2 0 -100 -50 0 50 100 150 Figure 12. Source-drain diode forward characteristics AM15698v1 VSD (V) 0 -100 TJ(°C) -50 0 50 100 150 TJ(°C) Figure 13. Output capacitance stored energy Eoss (µJ) AM15695v1 12 1 TJ=-50°C 10 0.9 8 0.8 TJ=25°C 6 0.7 4 TJ=150°C 0.6 2 0.5 0 2 4 6 8 10 ISD(A) DocID027200 Rev 2 0 0 100 200 300 400 500 600 700 800 VDS(V) 7/13 Electrical characteristics STFI13N80K5 Figure 14. Maximum avalanche energy vs. starting Tj AM15700v1 EAS (mJ) 140 120 100 80 60 40 20 0 0 8/13 20 40 60 80 100 120 140 TJ(°C) DocID027200 Rev 2 STFI13N80K5 3 Test circuits Test circuits Figure 15. Switching times test circuit for resistive load Figure 16. Gate charge test circuit VDD 12V 47kΩ 1kΩ 100nF 3.3 μF 2200 RL μF IG=CONST VDD VGS 100Ω Vi=20V=VGMAX VD RG 2200 μF D.U.T. D.U.T. VG 2.7kΩ PW 47kΩ 1kΩ PW AM01468v1 Figure 17. Test circuit for inductive load switching and diode recovery times A A AM01469v1 Figure 18. Unclamped inductive load test circuit L A D G D.U.T. FAST DIODE B B VD L=100μH S 3.3 μF B 25 Ω 1000 μF D VDD 2200 μF 3.3 μF VDD ID G RG S Vi D.U.T. Pw AM01470v1 AM01471v1 Figure 19. Unclamped inductive waveform Figure 20. Switching time waveform ton V(BR)DSS tdon VD toff tr tdoff tf 90% 90% IDM 10% ID VDD 10% 0 VDD VDS 90% VGS AM01472v1 0 DocID027200 Rev 2 10% AM01473v1 9/13 Package mechanical data 4 STFI13N80K5 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 21. I2PAKFP (TO-281) drawing UHY& 10/13 DocID027200 Rev 2 STFI13N80K5 Package mechanical data Table 9. I2PAKFP (TO-281) mechanical data mm Dim. Min. Typ. Max. A 4.40 - 4.60 B 2.50 2.70 D 2.50 2.75 D1 0.65 0.85 E 0.45 0.70 F 0.75 1.00 F1 1.20 G 4.95 5.20 H 10.00 10.40 L1 21.00 23.00 L2 13.20 14.10 L3 10.55 10.85 L4 2.70 3.20 L5 0.85 1.25 L6 7.50 7.60 DocID027200 Rev 2 7.70 11/13 Revision history 5 STFI13N80K5 Revision history Table 10. Document revision history 12/13 Date Revision Changes 25-Nov-2014 1 Initial release. 04-Dec-2014 2 Updated 4: Package mechanical data and Figure 1.: Internal schematic diagram Minor text changes. DocID027200 Rev 2 STFI13N80K5 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2014 STMicroelectronics – All rights reserved DocID027200 Rev 2 13/13