STF24N60M2
Datasheet
N-channel 600 V, 168 mΩ typ., 18 A MDmesh M2
Power MOSFET in a TO-220FP package
Features
1
2
3
TO-220FP
Order code
VDS @TJmax
RDS(on) max.
ID
STF24N60M2
650 V
190 mΩ
18 A
•
•
Extremely low gate charge
Excellent output capacitance (Coss) profile
•
•
100% avalanche tested
Zener-protected
D(2)
Applications
•
•
•
G(1)
Switching applications
LCC converters
Resonant converters
Description
S(3)
AM15572v1_no_tab
This device is an N-channel Power MOSFET developed using MDmesh M2
technology. Thanks to its strip layout and an improved vertical structure, the device
exhibits low on-resistance and optimized switching characteristics, rendering it
suitable for the most demanding high efficiency converters.
Product status link
STF24N60M2
Product summary
Order code
STF24N60M2
Marking
24N60M2
Package
TO-220FP
Packing
Tube
DS9402 - Rev 7 - February 2020
For further information contact your local STMicroelectronics sales office.
www.st.com
STF24N60M2
Electrical ratings
1
Electrical ratings
Table 1. Absolute maximum ratings
Symbol
Value
Unit
Gate-source voltage
±25
V
Drain current (continuous) at TC = 25 °C
18
A
Drain current (continuous) at TC = 100 °C
12
A
Drain current (pulsed)
72
A
Total power dissipation at TC = 25 °C
30
W
Peak diode recovery voltage slope
15
V/ns
MOSFET dv/dt ruggedness
50
V/ns
VISO
Insulation withstand voltage (RMS) from all three leads to external heat
sink (t = 1 s; TC = 25 °C)
2.5
kV
Tstg
Storage temperature range
-55 to 150
°C
Value
Unit
VGS
ID (1)
IDM
(2)
PTOT
dv/dt (3)
dv/dt
(4)
Tj
Parameter
Operating junction temperature range
1. Limited by maximum junction temperature.
2. Pulse width limited by safe operating area.
3. ISD ≤ 18 A, di/dt ≤ 400 A/µs; VDS(peak) < V(BR)DSS, VDD = 400 V
4. VDS ≤ 480 V
Table 2. Thermal data
Symbol
Parameter
Rthj-case
Thermal resistance junction-case
4.2
°C/W
Rthj-amb
Thermal resistance junction-ambient
62.5
°C/W
Value
Unit
3.5
A
180
mJ
Table 3. Avalanche characteristics
Symbol
IAR
EAS
DS9402 - Rev 7
Parameter
Avalanche current, repetitive or not repetitive
(pulse width limited by Tjmax)
Single pulse avalanche energy (starting Tj=25 °C, ID= IAR, VDD=50 V)
page 2/12
STF24N60M2
Electrical characteristics
2
Electrical characteristics
(TC = 25 °C unless otherwise specified).
Table 4. On /off states
Symbol
V(BR)DSS
IDSS
IGSS
VGS(th)
RDS(on)
Parameter
Drain-source breakdown
voltage
Zero gate voltage
drain current
Gate-body leakage
current
Gate threshold voltage
Static drain-source
on-resistance
Test conditions
ID = 1 mA, VGS = 0 V
Min.
Typ.
Max.
600
Unit
V
VGS = 0 V, VDS = 600 V
1
µA
VGS = 0 V, VDS = 600 V,
TC = 125 °C (1)
100
µA
VDS = 0 V, VGS = ± 25 V
±10
µA
3
4
V
168
190
mΩ
Min.
Typ.
Max.
Unit
-
1060
-
pF
-
55
-
pF
-
2.2
-
pF
-
258
-
pF
VDS = VGS, ID = 250 µA
2
VGS = 10 V, ID = 9 A
1. Defined by design, not subject to production test.
Table 5. Dynamic
Symbol
Parameter
Ciss
Input capacitance
Coss
Output capacitance
Crss
Reverse transfer capacitance
Coss eq. (1)
Test conditions
VDS = 100 V, f = 1 MHz,
VGS = 0 V
Equivalent output capacitance VDS = 0 to 480 V, VGS = 0 V
RG
Intrinsic gate resistance
f = 1 MHz, ID = 0 A
-
7
-
Ω
Qg
Total gate charge
VDD = 480 V, ID = 18 A,
-
29
-
nC
Qgs
Gate-source charge
-
6
-
nC
Qgd
Gate-drain charge
VGS = 0 to 10 V (see
Figure 14. Test circuit for gate
charge behavior)
-
12
-
nC
1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0
to 80% VDSS.
Table 6. Switching times
Symbol
td(on)
tr
td(off)
tf
DS9402 - Rev 7
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Turn-on delay time
VDD = 300 V, ID = 9 A,
-
14
-
ns
Rise time
RG = 4.7 Ω, VGS = 10 V
-
9
-
ns
Turn-off delay time
(see Figure 13. Test circuit for
resistive load switching times
and Figure 18. Switching time
waveform)
-
60
-
ns
-
15
-
ns
Fall time
page 3/12
STF24N60M2
Electrical characteristics
Table 7. Source-drain diode
Symbol
ISD (1)
ISDM
(2)
VSD (3)
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Source-drain current
-
18
A
Source-drain current (pulsed)
-
72
A
1.6
V
Forward on voltage
ISD = 18 A, VGS = 0 V
-
trr
Reverse recovery time
ISD = 18 A, di/dt = 100 A/µs
-
332
ns
Qrr
Reverse recovery charge
-
4
µC
IRRM
Reverse recovery current
VDD = 60 V (see
Figure 15. Test circuit for
inductive load switching and
diode recovery times)
-
24
A
trr
Reverse recovery time
ISD = 18 A, di/dt = 100 A/µs
-
450
ns
Qrr
Reverse recovery charge
VDD = 60 V, Tj = 150 °C
-
5.5
µC
Reverse recovery current
(see Figure 15. Test circuit for
inductive load switching and
diode recovery times)
-
25
A
IRRM
1. Limited by maximum junction temperature.
2. Pulse width limited by safe operating area.
3. Pulsed: pulse duration = 300 μs, duty cycle 1.5%.
DS9402 - Rev 7
page 4/12
STF24N60M2
Electrical characteristics (curves)
2.1
Electrical characteristics (curves)
Figure 1. Safe operating area
Figure 2. Thermal impedance
AM15462v1
)
on
D
S(
10
O
Li per
m at
ite io
d ni
by n
m this
ax a
R rea
is
ID
(A)
1
10µs
100µs
1ms
10ms
Tj=150°C
Tc=25°C
0.1
Single
pulse
0.01
0.1
10
1
VDS(V)
100
Figure 3. Output characteristics
Figure 4. Transfer characteristics
AM15470v1
ID
(A)
VGS= 8, 9, 10 V
VGS= 7 V
40
35
35
30
25
VGS= 6 V
20
20
15
15
10
10
VGS= 5 V
5
5
0
VGS= 4 V
0
10
5
20
15
VDS(V)
Figure 5. Gate charge vs gate-source voltage
AM15471v1
VDS
VGS
(V)
12 VDS
DS9402 - Rev 7
(V)
600
VDD=480 V
ID=18 A
10
500
8
400
6
300
4
200
2
100
0
VDS= 17 V
40
30
25
AM15469v1
ID
(A)
0
5
10
15
20
25
0
30 Qg (nC)
0
0
4
2
8
6
10 VGS(V)
Figure 6. Static drain-source on-resistance
RDS(on)
(mΩ)
AM15465v1
VGS=10V
176
172
168
164
160
0
4
8
12
16
ID(A)
page 5/12
STF24N60M2
Electrical characteristics (curves)
Figure 7. Capacitance variations
Figure 8. Output capacitance stored energy
AM15665v1
C
(pF)
Ciss
1000
AM15472v1
Eoss
(µJ)
8
7
6
5
100
Coss
10
4
3
2
1
Crss
1
0.1
1
100
10
VDS(V)
Figure 9. Normalized gate threshold voltage vs
temperature
AM15473v1
VGS(th)
(norm)
ID = 250 µA
1.1
0
0
100
200
300
400
500
600
VDS(V)
Figure 10. Normalized on-resistance vs temperature
AM15464v1
RDS(on)
(norm)
2.3
ID = 9 A
VGS = 10 V
2.1
1.9
1.0
1.7
1.5
0.9
1.3
0.8
1.1
0.9
0.7
0.7
0.6
-50
-25
25
0
50
75
100
TJ(°C)
Figure 11. Source-drain diode forward characteristics
AM15468v1
VSD
(V)
1.4
25
50
75 100
TJ(°C)
Figure 12. Normalized V(BR)DSS vs temperature
AM15466v1
V(BR)DSS
1.11
ID = 1mA
1.09
TJ=-50°C
1.07
1
1.05
0.8
1.03
1.01
0.6
TJ=150°C
0.4
TJ=25°C
0.99
0.97
0.2
0
0
(norm)
1.2
DS9402 - Rev 7
0.5
-50 -25
0.95
0
2
4
6
8
10 12 14 16
ISD(A)
0.93
-50 -25
0
25
50
75 100
TJ(°C)
page 6/12
STF24N60M2
Test circuits
3
Test circuits
Figure 13. Test circuit for resistive load switching times
Figure 14. Test circuit for gate charge behavior
VDD
12 V
2200
+ μF
3.3
μF
VDD
VD
VGS
1 kΩ
100 nF
RL
IG= CONST
VGS
RG
47 kΩ
+
pulse width
D.U.T.
2.7 kΩ
2200
μF
pulse width
D.U.T.
100 Ω
VG
47 kΩ
1 kΩ
AM01469v1
AM01468v1
Figure 15. Test circuit for inductive load switching and
diode recovery times
D
G
A
D.U.T.
S
25 Ω
A
L
A
B
B
3.3
µF
D
G
+
VD
100 µH
fast
diode
B
Figure 16. Unclamped inductive load test circuit
RG
1000
+ µF
2200
+ µF
VDD
3.3
µF
VDD
ID
D.U.T.
S
D.U.T.
Vi
_
pulse width
AM01471v1
AM01470v1
Figure 18. Switching time waveform
Figure 17. Unclamped inductive waveform
ton
V(BR)DSS
td(on)
VD
toff
td(off)
tr
tf
90%
90%
IDM
VDD
10%
0
ID
VDD
AM01472v1
VGS
0
VDS
10%
90%
10%
AM01473v1
DS9402 - Rev 7
page 7/12
STF24N60M2
Package information
4
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.
4.1
TO-220FP package information
Figure 19. TO-220FP package outline
7012510_Rev_13_B
DS9402 - Rev 7
page 8/12
STF24N60M2
TO-220FP package information
Table 8. TO-220FP package mechanical data
Dim.
mm
Min.
Max.
A
4.40
4.60
B
2.50
2.70
D
2.50
2.75
E
0.45
0.70
F
0.75
1.00
F1
1.15
1.70
F2
1.15
1.70
G
4.95
5.20
G1
2.40
2.70
H
10.00
10.40
L2
DS9402 - Rev 7
Typ.
16.00
L3
28.60
30.60
L4
9.80
10.60
L5
2.90
3.60
L6
15.90
16.40
L7
9.00
9.30
Dia
3.00
3.20
page 9/12
STF24N60M2
Revision history
Table 9. Document revision history
Date
Revision
Changes
10-Dec-2012
1
First release.
20-Dec-2012
2
Added MOSFET dv/dt ruggedness in Table 2: Absolute maximum ratings.
14-Jan-2013
3
Modified: Figure 16, 17
28-May-2013
4
– Modified: Figure 16, 17, 18 and 19
– Minor text changes
– Modified: Rthj-case value in Table 3
28-Feb-2014
5
– Modified: Figure 12
– Minor text changes
– Added: TO-3PF package
07-Apr-2014
6
– Added: Section 4.3: TO-3PF, STFW24N60M2
– Minor text changes
The part numbers STFI24N60M2 and STFW24N60M2 have been moved to a
separate datasheet.
19-Feb-2020
7
Removed maturity status indication from cover page. The document status is
production data.
Minor text changes.
DS9402 - Rev 7
page 10/12
STF24N60M2
Contents
Contents
1
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2
Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1
Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
4
Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4.1
TO-220FP package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
DS9402 - Rev 7
page 11/12
STF24N60M2
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DS9402 - Rev 7
page 12/12