STFI26NM60N

STFI26NM60N N-channel 600 V, 0.135 Ω typ., 20 A MDmesh™ II Power MOSFET in an I²PAKFP package Datasheet - production data Features  12 3    2 I PAKFP (TO-281) Figure 1: Internal schematic diagram Order code VDS RDS(on) max ID STFI26NM60N 600 V 0.165 Ω 20 A Fully insulated and low profile package with increased creepage path from pin to heatsink plate 100% avalanche tested Low input capacitance and gate charge Low gate input resistance Applications  Switching applications Description D(2) This device is an N-channel Power MOSFET developed using the second generation of MDmesh™ technology. This revolutionary Power MOSFET associates a vertical structure to the company’s strip layout to yield one of the world’s lowest on-resistance and gate charge. It is therefore suitable for the most demanding high efficiency converters. G(1) S(3) AM01475v1_no Tab_noZen Table 1: Device summary Order code Marking Package Packaging STFI26NM60N 26NM60N I²PAKFP (TO-281) Tube December 2016 DocID022495 Rev 4 This is information on a product in full production. 1/12 www.st.com Contents STFI26NM60N Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package information ....................................................................... 9 4.1 5 2/12 I²PAKFP package information ........................................................... 9 Revision history ............................................................................ 11 DocID022495 Rev 4 STFI26NM60N 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 600 V VGS Gate-source voltage ±30 V ID(1) Drain current (continuous) at TC = 25 °C 20 A ID(1) Drain current (continuous) at TC = 100 °C 12.6 A Drain current (pulsed) 80 A Total dissipation at TC = 25 °C 35 W Peak diode recovery voltage slope 15 V/ns 2500 V -55 to 150 °C Value Unit IDM (1)(2) PTOT dv/dt (3) VISO Insulation withstand voltage (RMS) from all three leads to external heat sink (t = 1 s; TC = 25 °C) Tstg Storage temperature range Tj Operating junction temperature range Notes: (1)Limited (2)Pulse (3)I SD by package. width limited by safe operating area. ≤ 20 A, di/dt ≤ 400 A/µs, VDS(peak) ≤ V(BR)DSS, VDD ≤ 80% V(BR)DSS Table 3: Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case 3.6 °C/W Rthj-amb Thermal resistance junction-ambient 62.5 °C/W Value Unit 6 A 610 mJ Table 4: Avalanche characteristics Symbol Parameter IAS Single pulse avalanche current (pulse width limited by Tjmax) EAS Single pulse avalanche energy (starting TJ=25 °C, ID=IAS, VDD=50 V) DocID022495 Rev 4 3/12 Electrical characteristics 2 STFI26NM60N Electrical characteristics (TCASE = 25 °C unless otherwise specified) Table 5: On/off states Symbol Parameter V(BR)DSS Drain-source breakdown voltage Test conditions ID = 1 mA, VGS = 0 V IDSS Zero gate voltage drain current IGSS Min. Typ. Max. 600 V VGS = 0 V, VDS = 600 V 1 VGS = 0 V, VDS = 600 V, TC= 125 °C (1) 100 Gate-body leakage current VDS = 0 V, VGS = ±25 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source onresistance VGS = 10 V, ID = 10 A Unit µA ±0.1 µA 3 4 V 0.135 0.165 Ω Min. Typ. Max. Unit - 1800 - pF - 115 - pF - 6 - pF VGS = 0 V, VDS = 0 to 480 V - 310 - pF - 60 - nC - 8.5 - nC - 30 - nC - 2.8 - Ω 2 Notes: (1)Defined by design, not subject to production test. Table 6: Dynamic Symbol Ciss Parameter Test conditions Input capacitance VDS = 50 V, f = 1 MHz, VGS = 0 V Coss Output capacitance Crss Reverse transfer capacitance Coss eq. (1) Equivalent output capacitance Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge VDD = 480 V, ID = 20 A, VGS = 10 V (see Figure 14: "Test circuit for gate charge behavior") RG Gate input resistance f=1 MHz, ID=0 A Notes: (1)C oss eq. is defined as a constant equivalent capacitance giving the same charging time as C oss when VDS increases from 0 to 80% VDS Table 7: Switching times Symbol td(on) tr td(off) tf 4/12 Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions Min. Typ. Max. Unit VDD = 300 V, ID = 10 A, RG = 4.7 Ω, VGS = 10 V (see Figure 13: "Test circuit for resistive load switching times" and Figure 18: "Switching time waveform") - 13 - ns - 25 - ns - 85 - ns - 50 - ns DocID022495 Rev 4 STFI26NM60N Electrical characteristics Table 8: Source-drain diode Symbol Parameter Test conditions ISD(1) Source-drain current ISDM(2) Source-drain current (pulsed) VSD(3) Forward on voltage trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current Min. Typ. Max. Unit - 20 A - 80 A ISD = 20 A, VGS = 0 V - 1.5 V ISD = 20 A, di/dt = 100 A/µs VDD = 60 V (see Figure 15: "Test circuit for inductive load switching and diode recovery times") - 370 ns - 5.8 µC - 31.6 A ISD = 20 A, di/dt = 100 A/µs VDD = 60 V, Tj = 150 °C (see Figure 15: "Test circuit for inductive load switching and diode recovery times") - 450 ns - 7.5 µC - 32.5 A Notes: (1)Limited (2) by package. Pulse width limited by safe operating area. (3)Pulsed: pulse duration = 300 µs, duty cycle 1.5% DocID022495 Rev 4 5/12 Electrical characteristics 2.1 STFI26NM60N Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance W 6/12 DocID022495 Rev 4 STFI26NM60N Electrical characteristics Figure 8: Capacitance variations Figure 9: Source-drain diode forward characteristics Figure 10: Normalized gate threshold voltage vs temperature Figure 11: Normalized on-resistance vs temperature Figure 12: Normalized V(BR)DSS vs temperature DocID022495 Rev 4 7/12 Test circuits 3 8/12 STFI26NM60N Test circuits Figure 13: Test circuit for resistive load switching times Figure 14: Test circuit for gate charge behavior Figure 15: Test circuit for inductive load switching and diode recovery times Figure 16: Unclamped inductive load test circuit Figure 17: Unclamped inductive waveform Figure 18: Switching time waveform DocID022495 Rev 4 STFI26NM60N 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 4.1 I²PAKFP package information Figure 19: I²PAKFP (TO-281) package outline 8291506 Re v. C DocID022495 Rev 4 9/12 Package information STFI26NM60N Table 9: I²PAKFP (TO-281) mechanical data mm Dim. Min. Typ. A 4.40 4.60 B 2.50 2.70 D 2.50 2.75 D1 0.65 0.85 E 0.45 0.70 F 0.75 1.00 F1 10/12 Max. 1.20 G 4.95 5.20 H 10.00 10.40 L1 21.00 23.00 L2 13.20 14.10 L3 10.55 10.85 L4 2.70 3.20 L5 0.85 L6 7.50 DocID022495 Rev 4 1.25 7.60 7.70 STFI26NM60N 5 Revision history Revision history Table 10: Document revision history Date Revision 15-Nov-2011 1 First release. 04-Jun-2012 2 Document status promoted from preliminary data to production data. Updated PTOT and Derating factor values in Table 2: Absolute maximum ratings, Rth-case value in Table 3: Thermal data Package name has been updated. 10-Jun-2015 3 Updated Section 4: Package information.Minor text changes. 4 Modified Table 2: "Absolute maximum ratings", Table 5: "On/off states", Table 6: "Dynamic" and Table 8: "Source-drain diode" Modified Section 2.1: "Electrical characteristics (curves)" Minor text changes 13-Dec-2016 Changes DocID022495 Rev 4 11/12 STFI26NM60N IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved 12/12 DocID022495 Rev 4