STFI40N60M2

STF40N60M2, STFI40N60M2, STFW40N60M2 N-channel 600 V, 0.078 Ω typ., 34 A MDmesh M2 Power MOSFETs in TO-220FP, I2PAKFP and TO-3PF packages Datasheet − production data Features Order codes VDS @ TJmax RDS(on) max ID 650 V 0.088 Ω 34 A STF40N60M2 STFI40N60M2 3 1 2 1 TO-220FP 2 STFW40N60M2 3 I2PAKFP (TO-281) • Extremely low gate charge • Excellent output capacitance (Coss) profile • 100% avalanche tested • Zener-protected  Applications  • Switching applications   • LLC converters, resonant converters TO-3PF Figure 1. Internal schematic diagram Description These devices are N-channel Power MOSFETs developed using MDmesh™ M2 technology. Thanks to their strip layout and improved vertical structure, the devices exhibit low on-resistance and optimized switching characteristics, rendering them suitable for the most demanding high efficiency converters. ' * 6 AM01476v1 Table 1. Device summary Order code Marking Packages STF40N60M2 STFI40N60M2 TO-220FP 40N60M2 I2PAKFP STFW40N60M2 September 2016 This is information on a product in full production. Packing (TO-281) Tube TO-3PF DocID026364 Rev 2 1/18 www.st.com Contents STF40N60M2, STFI40N60M2, STFW40N60M2 Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Test circuits 4 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 2/18 .............................................. 9 4.1 TO-220FP, package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.2 I2PAKFP (TO-281) package information . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.3 TO-3PF, package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 DocID026364 Rev 2 STF40N60M2, STFI40N60M2, STFW40N60M2 1 Electrical ratings Electrical ratings Table 2. Absolute maximum ratings Value Symbol Parameter VGS Gate-source voltage ID(1) ID (1) dv/dt (3) dv/dt(4) V Drain current (continuous) at TC = 25 °C 34 A Drain current (continuous) at TC = 100 °C 22 A 136 A Total dissipation at TC = 25 °C 40 63 W Peak diode recovery voltage slope 15 V/ns MOSFET dv/dt ruggedness 50 V/ns VISO Insulation withstand voltage (RMS) from all three leads to external heat sink (t=1 s; TC=25 °C) Tstg Storage temperature range Tj TO-3PF ± 25 IDM (1),(2) Drain current (pulsed) PTOT Unit TO-220FP, I2PAKFP 2500 3500 V °C - 55 to 150 Operating junction temperature range °C 1. Limited by maximum junction temperature 2. Pulse width limited by safe operating area. 3. ISD ≤ 34 A, di/dt ≤ 400 A/µs; VDS peak < V(BR)DSS, VDD=400 V. 4. VDS ≤ 480 V Table 3. Thermal data Value Symbol Parameter Unit TO-220FP, I2PAKFP TO-3PF Rthj-case Thermal resistance junction-case 3.13 2.00 °C/W Rthj-amb 62.5 50 °C/W Thermal resistance junction-ambient Table 4. Avalanche characteristics Symbol Parameter Value Unit IAR Avalanche current, repetitive or not repetitive (pulse width limited by Tjmax) 6 A EAS Single pulse avalanche energy (starting Tj=25°C, ID= IAR; VDD=50 V) 500 mJ DocID026364 Rev 2 3/18 18 Electrical characteristics 2 STF40N60M2, STFI40N60M2, STFW40N60M2 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 5. On /off states Symbol V(BR)DSS Parameter Drain-source breakdown voltage IDSS Zero gate voltage drain current () IGSS Gate-body leakage current Test conditions VGS = 0, ID = 1 mA Min. Typ. Max. Unit 600 V VGS = 0, VDS = 600 V 1 µA VGS = 0, VDS = 600 V, TC=125 °C(1) 100 µA VDS = 0, VGS = ± 25 V ±10 µA 3 4 V 0.078 0.088 Ω Min. Typ. Max. Unit - 2500 - pF - 117 - pF - 2.4 - pF VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source on-resistance 2 VGS = 10 V, ID = 17 A 1. Defined by design, not subject to production test Table 6. Dynamic Symbol Parameter Test conditions Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Coss eq.(1) Equivalent output capacitance VGS = 0, VDS = 0 to 480 V - 342 - pF RG Intrinsic gate resistance f = 1 MHz, ID = 0 - 4.4 - Ω Qg Total gate charge - 57 - nC Qgs Gate-source charge - 10 - nC Qgd Gate-drain charge VDD = 480 V, ID = 34 A, VGS = 10 V (see Figure 17: Gate charge test circuit) - 25.5 - nC VGS = 0, VDS = 100 V, f = 1 MHz 1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS 4/18 DocID026364 Rev 2 STF40N60M2, STFI40N60M2, STFW40N60M2 Electrical characteristics Table 7. Switching times Symbol td(on) tr Parameter Turn-on delay time Rise time td(off) tf Turn-off-delay time Fall time Test conditions Min. Typ. Max. Unit VDD = 300 V, ID = 34 A, RG = 4.7 Ω, VGS = 10 V (see Figure 16: Switching times test circuit for resistive load and Figure 21: Switching time waveform) - 20.5 - ns - 13.5 - ns - 96 - ns - 11 - ns Table 8. Source drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 34 A ISDM (1) Source-drain current (pulsed) - 136 A VSD (2) Forward on voltage ISD = 34 A, VGS = 0 - trr Reverse recovery time - 440 ns Qrr Reverse recovery charge - 8.2 µC IRRM Reverse recovery current ISD = 34 A, di/dt = 100 A/µs VDD = 60 V (see Figure 18: Test circuit for inductive load switching and diode recovery times) - 37 A - 568 ns - 11.5 µC - 40.5 A ISD trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ISD = 34 A, di/dt = 100 A/µs VDD = 60 V, Tj = 150 °C (see Figure 18: Test circuit for inductive load switching and diode recovery times) 1.6 V 1. Pulse width limited by safe operating area. 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5% DocID026364 Rev 2 5/18 18 Electrical characteristics 2.1 STF40N60M2, STFI40N60M2, STFW40N60M2 Electrical characteristics (curves) Figure 2. Safe operating area for TO-220FP and Figure 3. Thermal impedance for TO-220FP and I2PAKFP I2PAKFP AM16097v1 ID (A) 100 s ai are (on) s i DS th in ax R ion m at by r e d Op ite Lim 10 10µs 100µs 1ms 1 10ms 0.1 Tj=150°C Tc=25°C Single pulse 0.01 0.1 10 1 VDS(V) 100 Figure 4. Safe operating area for TO-3PF *,3*6$ ,' $ . *,3*6$ G    LV D H DU —V Q LV 6R WK 5' LQ D[ Q LR \P DW HU GE 2S LWH /LP      —V  PV  PV D    6LQJOHSXOVH  7M ƒ& 7F ƒ& 6LQJOHSXOVH      9'69 Figure 6. Output characteristics ID (A) 90     VGS=7, 8, 9, 10V           WSV AM16101v1 ID (A) VDS=18V 80 80 70 70 6V 60 60 50 50 40 40 30 30 5V 20 20 10 10 0   Figure 7. Transfer characteristics AM16100v1 6/18 Figure 5. Thermal impedance for TO-3PF 4V 0 5 10 15 20 VDS(V) DocID026364 Rev 2 0 0 2 4 6 8 10 VGS(V) STF40N60M2, STFI40N60M2, STFW40N60M2 Figure 8. Gate charge vs gate-source voltage AM16102v1 VDS VGS (V) 12 (V) VDD=480V ID=34A VDS 500 10 400 8 Electrical characteristics Figure 9. Static drain-source on-resistance AM16103v1 RDS(on) (Ω) VGS=10V 0.082 0.081 0.080 300 0.079 6 200 0.078 4 0.077 2 100 0 0 Qg(nC) 0.076 0 10 20 30 40 50 60 Figure 10. Capacitance variations 0 4 8 12 16 20 24 28 ID(A) Figure 11. Output capacitance stored energy AM16104v1 C (pF) 0.075 AM16105v1 Eoss (µJ) 10000 15 Ciss 1000 10 100 Coss 5 10 Crss 1 0.1 1 10 100 Figure 12. Normalized gate threshold voltage vs temperature AM15718v1 VGS(th) 0 0 VDS(V) (norm) 400 100 200 300 500 600 VDS(V) Figure 13. Normalized on-resistance vs temperature AM15719v1 RDS(on) (norm) ID=17 A 1.1 ID=250µA 2.1 1.0 1.7 0.9 1.3 0.8 0.9 0.7 0.6 -50 0 50 100 TJ(°C) DocID026364 Rev 2 0.5 -50 0 50 100 TJ(°C) 7/18 18 Electrical characteristics STF40N60M2, STFI40N60M2, STFW40N60M2 Figure 14. Normalized V(BR)DSS vs temperature AM15714v1 V(BR)DSS (norm) ID=1 mA Figure 15. Source-drain diode forward vs temperature GIPD240920132025FSR VSD (V) 1.1 TJ= -50°C 1 1.06 0.9 TJ= 25°C 1.02 0.8 0.98 0.7 TJ= 150°C 0.94 0.6 0.9 -50 8/18 0 50 100 TJ(°C) 0.5 0 DocID026364 Rev 2 6 12 18 24 30 ISD(A) STF40N60M2, STFI40N60M2, STFW40N60M2 3 Test circuits Test circuits Figure 16. Switching times test circuit for resistive load Figure 17. Gate charge test circuit VDD 12V 47kΩ 1kΩ 100nF 3.3 μF 2200 RL μF IG=CONST 2200 μF VD VGS RG 100Ω Vi=20V=VGMAX VDD D.U.T. VG 2.7kΩ D.U.T. 47kΩ PW 1kΩ PW AM01469v1 AM01468v1 Figure 18. Test circuit for inductive load switching and diode recovery times Figure 19. Unclamped inductive load test circuit L A A A VD D G D.U.T. FAST DIODE B B 2200 μF L=100μH S 3.3 μF B 25 Ω 1000 μF D 3.3 μF VDD ID VDD G Vi RG D.U.T. S Pw AM01471v1 AM01470v1 Figure 20. Unclamped inductive waveform Figure 21. Switching time waveform ton 9%5'66 tdon 9' toff tr tdoff tf 90% 90% ,'0 10% ,' 9'' 10% 0 9'' VDS 90% VGS $0Y 0 DocID026364 Rev 2 10% AM01473v1 9/18 18 Package information 4 STF40N60M2, STFI40N60M2, STFW40N60M2 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 10/18 DocID026364 Rev 2 STF40N60M2, STFI40N60M2, STFW40N60M2 4.1 Package information TO-220FP, package information Figure 22. TO-220FP package outline 7012510_Rev_K_B DocID026364 Rev 2 11/18 18 Package information STF40N60M2, STFI40N60M2, STFW40N60M2 Table 9. TO-220FP mechanical data mm Dim. Min. Typ. A 4.4 4.6 B 2.5 2.7 D 2.5 2.75 E 0.45 0.7 F 0.75 1 F1 1.15 1.70 F2 1.15 1.70 G 4.95 5.2 G1 2.4 2.7 H 10 10.4 L2 12/18 Max. 16 L3 28.6 30.6 L4 9.8 10.6 L5 2.9 3.6 L6 15.9 16.4 L7 9 9.3 Dia 3 3.2 DocID026364 Rev 2 STF40N60M2, STFI40N60M2, STFW40N60M2 4.2 Package information I2PAKFP (TO-281) package information Figure 23. I2PAK(TO-281) package outline 5HY& DocID026364 Rev 2 13/18 18 Package information STF40N60M2, STFI40N60M2, STFW40N60M2 Table 10. I2PAKFP (TO-281) package mechanical data mm Dim. Min. Typ. Max. A 4.40 - 4.60 B 2.50 2.70 D 2.50 2.75 D1 0.65 0.85 E 0.45 0.70 F 0.75 1.00 F1 14/18 1.20 G 4.95 5.20 H 10.00 10.40 L1 21.00 23.00 L2 13.20 14.10 L3 10.55 10.85 L4 2.70 3.20 L5 0.85 1.25 L6 7.50 7.60 DocID026364 Rev 2 7.70 STF40N60M2, STFI40N60M2, STFW40N60M2 4.3 Package information TO-3PF, package information Figure 24. TO-3PF package outline B' DocID026364 Rev 2 15/18 18 Package information STF40N60M2, STFI40N60M2, STFW40N60M2 Table 11. TO-3PF package mechanical data mm Dim. Min. Typ. A 5.30 5.70 C 2.80 3.20 D 3.10 3.50 D1 1.80 2.20 E 0.80 1.10 F 0.65 0.95 F2 1.80 2.20 G 10.30 11.50 G1 16/18 Max. 5.45 H 15.30 15.70 L 9.80 L2 22.80 23.20 L3 26.30 26.70 L4 43.20 44.40 L5 4.30 4.70 L6 24.30 24.70 L7 14.60 15 N 1.80 2.20 R 3.80 4.20 Dia 3.40 3.80 10 DocID026364 Rev 2 10.20 STF40N60M2, STFI40N60M2, STFW40N60M2 5 Revision history Revision history Table 12. Document revision history Date Revision 15-May-2014 1 First release. Part numbers STF40N60M2 and STFI40N60M2 previously included in datasheet DocID024932. 2 Updated title in cover page. Updated Table 2: Absolute maximum ratings, Table 5: On /off states,Table 6: Dynamic and Table 8: Source drain diode. Minor text changes. 28-Sep-2016 Changes DocID026364 Rev 2 17/18 18 STF40N60M2, STFI40N60M2, STFW40N60M2 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved 18/18 DocID026364 Rev 2