STFI5N95K3
N-channel 950 V, 3 Ω typ., 4 A Zener-protected SuperMESH3™
Power MOSFET in I2PAKFP package
Datasheet − production data
Features
1
2
Order code
VDS
RDS(on) max
ID
PTOT
STFI5N95K3
950 V
3.5 Ω
4A
25 W
• Fully insulated and low profile package with
increased creepage path from pin to heatsink
plate
3
• 100% avalanche tested
I2PAKFP
(TO-281)
• Extremely large avalanche performance
• Gate charge minimized
• Very low intrinsic capacitances
Figure 1. Internal schematic diagram
'
• Zener-protected
Applications
• Switching applications
Description
*
6
AM01476v1
This SuperMESH3™ Power MOSFET is the
result of improvements applied to
STMicroelectronics’ SuperMESH™ technology,
combined with a new optimized vertical structure.
This device boasts an extremely low onresistance, superior dynamic performance and
high avalanche capability, rendering it suitable for
the most demanding applications.
Table 1. Device summary
Order code
Marking
Package
Packaging
STFI5N95K3
5N95K3
I2PAKFP (TO-281)
Tube
May 2013
This is information on a product in full production.
DocID023624 Rev 1
1/13
www.st.com
13
Contents
STFI5N95K3
Contents
1
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
Test circuits
4
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2/13
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STFI5N95K3
1
Electrical ratings
Electrical ratings
Table 2. Absolute maximum ratings
Symbol
VGS
ID
ID
Parameter
Gate- source voltage
Drain current (continuous) at TC = 25 °C
Value
Unit
±30
V
(1)
A
(1)
4
Drain current (continuous) at TC = 100 °C
3
A
IDM (2)
Drain current (pulsed)
16(1)
A
PTOT
Total dissipation at TC = 25 °C
25
W
IAR
Avalanche current, repetitive or notrepetitive (pulse width limited by TJ max)
4
A
EAS
Single pulse avalanche energy
(starting TJ = 25 °C, ID = IAR, VDD = 50 V)
100
mJ
5
V/ns
2500
V
-55 to 150
°C
Value
Unit
5
°C/W
62.5
°C/W
dv/dt(3)
Peak diode recovery voltage slope
VISO
Insulation withstand voltage (RMS) from all
three leads to external heat sink
(t = 1 s,TC = 25 °C)
TJ
Tstg
Operating junction temperature
Storage temperature
1. Limited by maximum junction temperature
2. Pulse width limited by safe operating area
3. ISD ≤ 4 A, di/dt ≤ 100 A/µs, peak VDS ≤ V(BR)DSS
Table 3. Thermal data
Symbol
Parameter
Rthj-case
Thermal resistance junction-case max
Rthj-amb
Thermal resistance junction-ambient max
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Electrical characteristics
2
STFI5N95K3
Electrical characteristics
(Tcase =25 °C unless otherwise specified)
Table 4. On /off states
Symbol
V(BR)DSS
Parameter
Test conditions
Drain-source
breakdown voltage
ID = 1 mA, VGS = 0
Min.
Typ.
Max.
Unit
950
V
IDSS
Zero gate voltage
VDS = 950 V
drain current (VGS = 0) VDS = 950 V, TC=125 °C
1
50
µA
µA
IGSS
Gate-body leakage
current (VDS = 0)
±10
µA
4
5
V
3
3.5
Ω
Min.
Typ.
Max.
Unit
-
460
-
pF
-
38
-
pF
-
1
-
pF
VGS = ± 20 V
VGS(th)
Gate threshold voltage VDS = VGS, ID = 100 µA
RDS(on)
Static drain-source onVGS = 10 V, ID = 2 A
resistance
3
Table 5. Dynamic
Symbol
Parameter
Test conditions
Ciss
Input capacitance
Coss
Output capacitance
Crss
Reverse transfer
capacitance
Co(tr)(1)
Equivalent
capacitance time
related
VDS = 0 to 760 V, VGS = 0
-
970
-
pF
Co(er)(2)
Equivalent
capacitance energy
related
VDS = 0 to 760 V, VGS = 0
-
15
-
pF
Rg
Gate input resistance
f=1 MHz open drain
-
5.5
-
Ω
Qg
Total gate charge
-
19
-
nC
Qgs
Gate-source charge
-
4.7
-
nC
Qgd
Gate-drain charge
VDD = 760 V, ID = 4 A,
VGS = 10 V
(see Figure 16)
-
12
-
nC
VDS = 25 V, f = 1 MHz,
VGS = 0
1. Time related is defined as a constant equivalent capacitance giving the same charging time as Coss when
VDS increases from 0 to 80% VDSS
2. Energy related is defined as a constant equivalent capacitance giving the same stored energy as Coss
when VDS increases from 0 to 80% VDSS
4/13
DocID023624 Rev 1
STFI5N95K3
Electrical characteristics
Table 6. Switching times
Symbol
td(on)
tr
Parameter
Test conditions
Turn-on delay time
VDD = 475 V, ID = 2 A,
RG = 4.7 Ω, VGS = 10 V
(see Figure 15)
Rise time
td(off)
tf
Turn-off delay time
Fall time
Min.
Typ.
Max. Unit
-
17
-
ns
-
7
-
ns
-
32
-
ns
-
18
-
ns
Table 7. Source drain diode
Symbol
ISD
ISDM (1)
VSD
(2)
Parameter
Test conditions
Min. Typ. Max. Unit
Source-drain current
-
4
A
Source-drain current (pulsed)
-
16
A
1.6
V
Forward on voltage
ISD = 4 A, VGS = 0
-
trr
Reverse recovery time
-
410
ns
Qrr
Reverse recovery charge
-
3.5
µC
IRRM
Reverse recovery current
ISD = 4 A, di/dt = 100 A/µs
VDD= 60 V
(see Figure 17)
-
17
A
ISD = 4 A, di/dt = 100 A/µs
VDD= 60 V TJ = 150 °C
(see Figure 17)
-
516
ns
-
4.1
µC
-
16
A
trr
Reverse recovery time
Qrr
Reverse recovery charge
IRRM
Reverse recovery current
1. Pulse width limited by safe operating area
2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%
Table 8. Gate-source Zener diode
Symbol
V(BR)GSO
Parameter
Test conditions
Gate-source breakdown
voltage
IGS= ± 1 mA, ID=0
Min.
Typ.
30
-
Max. Unit
-
V
The built-in back-to-back Zener diodes have specifically been designed to enhance not only
the device’s ESD capability, but also to make them safely absorb possible voltage transients
that may occasionally be applied from gate to source. In this respect the Zener voltage is
appropriate to achieve an efficient and cost-effective intervention to protect the device’s
integrity. These integrated Zener diodes thus avoid the usage of external components.
DocID023624 Rev 1
5/13
Electrical characteristics
2.1
STFI5N95K3
Electrical characteristics (curves)
Figure 2. Safe operating area
Figure 3. Thermal impedance
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Figure 4. Output characteristics
Figure 5. Transfer characteristics
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Figure 7. Static drain-source on-resistance
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Figure 6. Gate charge vs gate-source voltage
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DocID023624 Rev 1
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STFI5N95K3
Electrical characteristics
Figure 8. Capacitance variations
Figure 9. Output capacitance stored energy
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Figure 10. Normalized gate threshold voltage vs
temperature
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Figure 11. Normalized on-resistance vs
temperature
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Figure 12. Source-drain diode forward
characteristics
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Figure 13. Normalized BVDSS vs temperature
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DocID023624 Rev 1
7-&
7/13
Electrical characteristics
STFI5N95K3
Figure 14. Maximum avalanche energy vs
starting Tj
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9'' 9
8/13
7-&
DocID023624 Rev 1
STFI5N95K3
3
Test circuits
Test circuits
Figure 15. Switching times test circuit for
resistive load
Figure 16. Gate charge test circuit
VDD
12V
47kΩ
1kΩ
100nF
3.3
μF
2200
RL
μF
VGS
IG=CONST
VDD
100Ω
Vi=20V=VGMAX
VD
RG
2200
μF
D.U.T.
D.U.T.
VG
2.7kΩ
PW
47kΩ
1kΩ
PW
AM01468v1
Figure 17. Test circuit for inductive load
switching and diode recovery times
A
A
D.U.T.
FAST
DIODE
B
B
AM01469v1
Figure 18. Unclamped inductive load test circuit
L
A
D
G
VD
L=100μH
S
3.3
μF
B
25 Ω
1000
μF
D
VDD
2200
μF
3.3
μF
VDD
ID
G
RG
S
Vi
D.U.T.
Pw
AM01470v1
AM01471v1
Figure 19. Unclamped inductive waveform
Figure 20. Switching time waveform
ton
V(BR)DSS
tdon
VD
toff
tr
tdoff
tf
90%
90%
IDM
10%
ID
VDD
10%
0
VDD
VDS
90%
VGS
AM01472v1
0
DocID023624 Rev 1
10%
AM01473v1
9/13
Package mechanical data
4
STFI5N95K3
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
10/13
DocID023624 Rev 1
STFI5N95K3
Package mechanical data
Table 9. I2PAKFP (TO-281) mechanical data
mm
Dim.
Min.
Typ.
Max.
A
4.40
4.60
B
2.50
2.70
D
2.50
2.75
D1
0.65
0.85
E
0.45
0.70
F
0.75
1.00
F1
1.20
G
4.95
H
10.00
10.40
L1
21.00
23.00
L2
13.20
14.10
L3
10.55
10.85
L4
2.70
3.20
L5
0.85
1.25
L6
7.30
7.50
-
5.20
Figure 21. I2PAKFP (TO-281) drawing
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DocID023624 Rev 1
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Revision history
5
STFI5N95K3
Revision history
Table 10. Document revision history
12/13
Date
Revision
09-May-2013
1
Changes
First release
DocID023624 Rev 1
STFI5N95K3
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