STFI7LN80K5
N-channel 800 V, 0.95 Ω typ., 5 A MDmesh™ K5
Power MOSFET in a I²PAKFP package
Datasheet - production data
Features
12
3
I 2 PAKFP
(TO-281)
Order code
VDS
RDS(on) max.
ID
STFI7LN80K5
800 V
1.15 Ω
5A
Industry’s lowest RDS(on) x area
Industry’s best figure of merit (FoM)
Ultra-low gate charge
100% avalanche tested
Zener-protected
Applications
Figure 1: Internal schematic diagram
D(2)
Switching applications
Description
This very high voltage N-channel Power
MOSFET is designed using MDmesh™ K5
technology based on an innovative proprietary
vertical structure. The result is a dramatic
reduction in on-resistance and ultra-low gate
charge for applications requiring superior power
density and high efficiency.
G(1)
S(3)
AM15572v1_no_tab
Table 1: Device summary
Order code
Marking
Package
Packing
STFI7LN80K5
7LN80K5
I²PAKFP (TO-281)
Tube
December 2015
DocID028783 Rev 1
This is information on a product in full production.
1/12
www.st.com
Contents
STFI7LN80K5
Contents
1
Electrical ratings ............................................................................. 3
2
Electrical characteristics ................................................................ 4
2.1
Electrical characteristics (curves) ...................................................... 6
3
Test circuits ..................................................................................... 8
4
Package information ....................................................................... 9
4.1
5
2/12
I²PAKFP (TO-281) package information ........................................... 9
Revision history ............................................................................ 11
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STFI7LN80K5
1
Electrical ratings
Electrical ratings
Table 2: Absolute maximum ratings
Symbol
VGS
Parameter
Gate-source voltage
Value
Unit
± 30
V
ID
Drain current (continuous) at TC = 25 °C
5
A
(1)
ID
Drain current (continuous) at TC = 100 °C
3.4
A
(2)
ID
Drain current (pulsed)
20
A
PTOT
Total dissipation at TC = 25 °C
25
W
VISO
Insulation withstand voltage (RMS) from all three leads to
external heat sink (t=1 s; TC=25 °C)
2500
V
(1)
dv/dt
(3)
Peak diode recovery voltage slope
4.5
dv/dt
(4)
MOSFET dv/dt ruggedness
50
Tstg
Storage temperature
TJ
Operating junction temperature
- 55 to 150
V/ns
°C
Notes:
(1)
(2)
Limited by maximum junction temperature.
Pulse width limited by safe operating area.
(3)
ISD ≤ 5 A, di/dt 100 A/μs; VDS peak < V(BR)DSS,VDD= 640 V
(4)
VDS ≤ 640 V
Table 3: Thermal data
Symbol
Parameter
Rthj-case
Thermal resistance junction-case
Rthj-amb
Thermal resistance junction-ambient
Value
Unit
5
°C/W
62.5
°C/W
Table 4: Avalanche characteristics
Symbol
Parameter
Value
Unit
IAR
Avalanche current, repetitive or not repetitive (pulse width limited
by Tjmax)
1.5
A
EAS
Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR,
VDD = 50 V)
200
mJ
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Electrical characteristics
2
STFI7LN80K5
Electrical characteristics
TC = 25 °C unless otherwise specified
Table 5: On/off-state
Symbol
V(BR)DSS
Parameter
Drain-source breakdown voltage
Test conditions
Min.
VGS = 0 V, ID = 1 mA
800
Typ.
Max.
Unit
V
VGS = 0 V, VDS = 800 V
1
µA
IDSS
Zero gate voltage drain current
VGS = 0 V, VDS = 800 V
TC = 125 °C
50
µA
IGSS
Gate body leakage current
VDS = 0 V, VGS = ±20 V
±10
µA
VGS(th)
Gate threshold voltage
VDS = VGS, ID = 100 µA
4
5
V
RDS(on)
Static drain-source on-resistance
VGS = 10 V, ID = 2.5 A
0.95
1.15
Ω
Min.
Typ.
Max.
Unit
-
270
-
pF
-
22
-
pF
-
0.5
-
pF
-
17
-
nC
-
48
-
nC
3
Table 6: Dynamic
Symbol
Ciss
Parameter
Test conditions
Input capacitance
VDS = 100 V, f = 1 MHz,
VGS = 0 V
Coss
Output capacitance
Crss
Reverse transfer capacitance
(1)
Co(er)
(2)
Co(tr)
Equivalent capacitance energy
related
Equivalent capacitance time
related
VDS = 0 to 640 V, VGS = 0
V
Rg
Intrinsic gate resistance
f = 1 MHz, ID=0 A
-
7.5
-
Ω
Qg
Total gate charge
-
12
-
nC
Qgs
Gate-source charge
-
2.6
-
nC
Qgd
Gate-drain charge
VDD = 640 V, ID = 5 A
VGS= 10 V
See (Figure 15: "Test
circuit for gate charge
behavior")
-
8.6
-
nC
Notes:
(1)
Energy related is defined as a constant equivalent capacitance giving the same stored energy as C oss when VDS
increases from 0 to 80% VDSS
(2)
Time related is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS
increases from 0 to 80% VDSS
Table 7: Switching times
Symbol
td(on)
tr
td(off)
tf
4/12
Parameter
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Test conditions
VDD= 400 V, ID =2.5 A, RG = 4.7 Ω
VGS = 10 V
See (Figure 14: "Test circuit for
resistive load switching times" and
Figure 19: "Switching time
waveform")
DocID028783 Rev 1
Min.
Typ.
Max.
Unit
-
9.3
-
ns
-
6.7
-
ns
-
23.6
-
ns
-
17.4
-
ns
STFI7LN80K5
Electrical characteristics
Table 8: Source-drain diode
Symbol
ISD
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Source-drain current
-
5
A
(1)
Source-drain current
(pulsed)
-
20
A
(2)
Forward on voltage
-
1.6
V
ISDM
VSD
ISD = 5 A, VGS = 0 V
trr
Reverse recovery time
Qrr
Reverse recovery
charge
IRRM
Reverse recovery
current
trr
Reverse recovery time
Qrr
Reverse recovery
charge
IRRM
Reverse recovery
current
ISD = 5 A, di/dt = 100 A/µs,
VDD = 60 V
See Figure 16: "Test circuit for
inductive load switching and diode
recovery times"
ISD = 5 A, di/dt = 100 A/µs
VDD = 60 V, Tj = 150 °C
See Figure 16: "Test circuit for
inductive load switching and diode
recovery times"
-
276
ns
-
2.13
µC
-
15.4
A
-
402
ns
-
2.79
µC
-
13.9
A
Notes:
(1)
(2)
Pulse width limited by safe operating area
Pulsed: pulse duration = 300 µs, duty cycle 1.5%
Table 9: Gate-source Zener diode
Symbol
V(BR)GSO
Parameter
Gate-source breakdown voltage
Test conditions
IGS= ± 1mA, ID= 0 A
Min.
Typ.
Max.
Unit
30
-
-
V
The built-in back-to-back Zener diodes are specifically designed to enhance the ESD
performance of the device. The Zener voltage facilitates efficient and cost-effective device
integrity protection,thus eliminating the need for additional external componentry.
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Electrical characteristics
2.2
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STFI7LN80K5
Electrical characteristics (curves)
Figure 2: Safe operating area
Figure 3: Thermal impedance
Figure 4: Output characteristics
Figure 5: Transfer characteristics
Figure 6: Gate charge vs gate-source voltage
Figure 7: Static drain-source on-resistance
DocID028783 Rev 1
STFI7LN80K5
Electrical characteristics
Figure 8: Capacitance variations
Figure 9: Normalized gate threshold voltage
vs temperature
Figure 10: Normalized V(BR)DSS vs temperature
Figure 11: Normalized on-resistance vs
temperature
Figure 12: Source-drain diode forward
characteristics
Figure 13: Maximum avalanche energy vs
starting TJ
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Test circuits
3
8/12
STFI7LN80K5
Test circuits
Figure 14: Test circuit for resistive load
switching times
Figure 15: Test circuit for gate charge
behavior
Figure 16: Test circuit for inductive load
switching and diode recovery times
Figure 17: Unclamped inductive load test
circuit
Figure 18: Unclamped inductive waveform
Figure 19: Switching time waveform
DocID028783 Rev 1
STFI7LN80K5
4
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
4.1
I²PAKFP (TO-281) package information
Figure 20: I²PAKFP (TO-281) package outline
8291506 Re v. C
DocID028783 Rev 1
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Package information
STFI7LN80K5
Table 10: I²PAKFP (TO-281) mechanical data
mm
Dim.
Min.
Typ.
A
4.40
4.60
B
2.50
2.70
D
2.50
2.75
D1
0.65
0.85
E
0.45
0.70
F
0.75
1.00
F1
10/12
Max.
1.20
G
4.95
5.20
H
10.00
10.40
L1
21.00
23.00
L2
13.20
14.10
L3
10.55
10.85
L4
2.70
3.20
L5
0.85
L6
7.50
DocID028783 Rev 1
1.25
7.60
7.70
STFI7LN80K5
5
Revision history
Revision history
Table 11: Document revision history
Date
Revision
15-Dec-2015
1
DocID028783 Rev 1
Changes
First release.
11/12
STFI7LN80K5
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DocID028783 Rev 1
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