STFU15N80K5

STFU15N80K5 Datasheet N-channel 800 V, 300 mΩ typ., 14 A MDmesh K5 Power MOSFET in a TO-220FP ultra narrow leads package Features 1 2 3 TO-220FP ultra narrow leads D(2) Order code VDS RDS(on ) max. ID STFU15N80K5 800 V 375 mΩ 14 A • Industry’s lowest RDS(on) x area • • • • Industry’s best FoM (figure of merit) Ultra-low gate charge 100% avalanche tested Zener-protected Applications • G(1) Switching applications Description S(3) AM15572v1_no_tab This very high voltage N-channel Power MOSFET is designed using MDmesh K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency. Product status link STFU15N80K5 Product summary Order code STFU15N80K5 Marking 15N80K5 Package TO-220FP ultra narrow leads Packing Tube DS10950 - Rev 3 - May 2020 For further information contact your local STMicroelectronics sales office. www.st.com STFU15N80K5 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Parameter Value Unit ± 30 V VGS Gate-source voltage ID (1) Drain current (continuous) at TC = 25 °C 14 A ID (1) Drain current (continuous) at TC = 100 °C 8.8 A IDM (2) Drain current (pulsed) 56 A PTOT Total power dissipation at TC = 25 °C 35 W VISO Insulation withstand voltage (RMS) from all three leads to external heat sink (t=1 s; TC=25 °C) 2500 V 4.5 V/ns - 55 to 150 °C Value Unit dv/dt (3) Tstg TJ Peak diode recovery voltage slope Storage temperature range Operating junction temperature range 1. Limited by package. 2. Pulse width limited by safe operating area. 3. ISD ≤ 14 A, di/dt = 100 A/μs; VDS (peak) < V(BR)DSS. Table 2. Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case 4.17 °C/W Rthj-amb Thermal resistance junction-ambient 62.5 °C/W Value Unit 4 A 150 mJ Table 3. Avalanche characteristics Symbol DS10950 - Rev 3 Parameter IAR Avalanche current, repetitive or not repetitive (pulse width limited by Tjmax) EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) page 2/13 STFU15N80K5 Electrical characteristics 2 Electrical characteristics TC = 25 °C unless otherwise specified. Table 4. On/off-state Symbol V(BR)DSS Parameter Drain-source breakdown voltage Test conditions VGS = 0 V, ID = 1 mA Min. Typ. 800 IDSS 1 µA 50 µA ±10 µA 4 5 V 300 375 mΩ Min. Typ. Max. Unit - 1100 - pF - 85 - pF - 1.5 - pF - 113 - pF - 49 - pF VGS = 0 V, VDS = 800 V TC = 125 °C(1) IGSS Gate body leakage current VDS = 0 V, VGS = ±20 V VGS(th) Gate threshold voltage VDS = VGS, ID = 100 µA RDS(on) Static drain-source onresistance VGS = 10 V, ID = 7 A Unit V VGS = 0 V, VDS = 800 V Zero gate voltage drain current Max. 3 1. Defined by design, not subject to production test. Table 5. Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Co(tr) (1) Equivalent capacitance time related Test conditions VDS = 100 V, f = 1 MHz, VGS = 0 V VDS = 0 to 640 V, VGS = 0 V Co(er) (2) Equivalent capacitance energy related Rg Intrinsic gate resistance f = 1 MHz , ID= 0 A - 4.5 - Ω Qg Total gate charge VDD = 640 V, ID = 12 A - 32 - nC Qgs Gate-source charge VGS= 0 to 10 V - 6 - nC Qgd Gate-drain charge (see Figure 15. Test circuit for gate charge behavior) - 22 - nC 1. Time related is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS 2. Energy related is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS increases from 0 to 80% VDSS Table 6. Switching times Symbol td(on) tr td(off) tf DS10950 - Rev 3 Parameter Min. Typ. Max. Unit VDD= 400 V, ID =7 A, RG = 4.7 Ω - 19 - ns Rise time VGS = 10 V - 17.6 - ns Turn-off delay time see ( Figure 14. Test circuit for resistive load switching times and Figure 19. Switching time waveform) - 44 - ns - 10 - ns Turn-on delay time Fall time Test conditions page 3/13 STFU15N80K5 Electrical characteristics Table 7. Source-drain diode Symbol ISD Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 14 A ISDM (1) Source-drain current (pulsed) - 56 A VSD (2) Forward on voltage - 1.5 V trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current trr Qrr IRRM ISD = 14 A, VGS = 0 V - 445 ns (see Figure 16. Test circuit for inductive load switching and diode recovery times) - 8.2 µC - 37 A Reverse recovery time ISD = 14 A, di/dt = 100 A/µs VDD = 60 V, - 580 ns Reverse recovery charge Tj = 150 °C - 10 µC Reverse recovery current (see Figure 16. Test circuit for inductive load switching and diode recovery times) - 35 A ISD = 14 A, di/dt = 100 A/µs,VDD = 60 V 1. Pulse width limited by safe operating area 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5% Table 8. Gate-source Zener diode Symbol V(BR)GSO Parameter Gate-source breakdown voltage Test conditions IGS= ± 1mA, ID= 0 A Min. Typ. Max. Unit 30 - - V The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection,thus eliminating the need for additional external componentry. DS10950 - Rev 3 page 4/13 STFU15N80K5 Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Figure 2. Thermal impedance Figure 1. Safe operating area GC20521 K δ=0.5 0.2 10-1 0.1 0.05 0.02 0.01 10-2 Zth= K*R thJ-c δ =t p/Ƭ Single pulse tp 10-3 10-4 10 -3 10 10 -2 -1 Ƭ 10-0 tp(s) Figure 3. Output characteristics Figure 4. Transfer characteristics Figure 5. Gate charge vs gate-source voltage Figure 6. Static drain-source on-resistance GIPD230320151105MT VDS VGS (V) 12 VDS (V) 600 VDD=640 V ID=14 A 10 500 8 400 6 300 4 200 2 100 0 DS10950 - Rev 3 0 5 10 15 20 25 0 30 Qg (nC) RDS(on) (mΩ) 330 GIPD230320151106MT VGS = 10 V 320 310 300 290 280 270 0 2 4 6 8 10 12 14 ID (A) page 5/13 STFU15N80K5 Electrical characteristics (curves) Figure 7. Capacitance variations Figure 8. Source-drain diode forward characteristics Figure 9. Normalized gate threshold voltage vs temperature Figure 10. Normalized on-resistance vs temperature Figure 11. Output capacitance stored energy Figure 12. Normalized VDS vs temperature DS10950 - Rev 3 page 6/13 STFU15N80K5 Electrical characteristics (curves) Figure 13. Maximum avalanche energy vs temperature DS10950 - Rev 3 page 7/13 STFU15N80K5 Test circuits 3 Test circuits Figure 14. Test circuit for resistive load switching times Figure 15. Test circuit for gate charge behavior VDD 12 V 2200 + μF 3.3 μF VDD VD VGS 1 kΩ 100 nF RL IG= CONST VGS RG 47 kΩ + pulse width D.U.T. 2.7 kΩ 2200 μF pulse width D.U.T. 100 Ω VG 47 kΩ 1 kΩ AM01469v1 AM01468v1 Figure 16. Test circuit for inductive load switching and diode recovery times D G A D.U.T. S 25 Ω A L A B B 3.3 µF D G + VD 100 µH fast diode B Figure 17. Unclamped inductive load test circuit RG 1000 + µF 2200 + µF VDD 3.3 µF VDD ID D.U.T. S D.U.T. Vi _ pulse width AM01471v1 AM01470v1 Figure 19. Switching time waveform Figure 18. Unclamped inductive waveform ton V(BR)DSS td(on) VD toff td(off) tr tf 90% 90% IDM VDD 10% 0 ID VDD AM01472v1 VGS 0 VDS 10% 90% 10% AM01473v1 DS10950 - Rev 3 page 8/13 STFU15N80K5 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 4.1 TO-220FP ultra narrow leads package information Figure 20. TO-220FP ultra narrow leads package outline DS10950 - Rev 3 page 9/13 STFU15N80K5 TO-220FP ultra narrow leads package information Table 9. TO-220FP ultra narrow leads mechanical data Dim. DS10950 - Rev 3 mm Min. Typ. Max. A 4.40 4.60 B 2.50 2.70 D 2.50 2.75 E 0.45 0.60 F 0.65 0.75 F1 - 0.90 G 4.95 5.20 G1 2.40 H 10.00 10.40 L2 15.10 15.90 L3 28.50 30.50 L4 10.20 11.00 L5 2.50 3.10 L6 15.60 16.40 L7 9.00 9.30 L8 3.20 3.60 L9 - 1.30 Dia. 3.00 3.20 2.54 2.70 page 10/13 STFU15N80K5 Revision history Table 10. Document revision history Date Revision 13-Apr-2015 1 09-Sep-2015 2 Changes Initial release. Text and formatting changes throughout document Datasheet status promoted from preliminary to production data Updated internal schematic diagram on cover page. 15-May-2020 3 Modified Figure 6. Static drain-source on-resistance . Updated Section 4.1 TO-220FP ultra narrow leads package information. Minor text changes. DS10950 - Rev 3 page 11/13 STFU15N80K5 Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4.1 TO-220FP ultra narrow leads package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 DS10950 - Rev 3 page 12/13 STFU15N80K5 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2020 STMicroelectronics – All rights reserved DS10950 - Rev 3 page 13/13