STFU18N65M2

STFU18N65M2 N-channel 650 V, 0.275 Ω typ., 12 A MDmesh™ M2 Power MOSFET in a TO-220FP ultra narrow leads package Datasheet - production data Features 1 2     3 Order code VDS RDS(on) max ID STFU18N65M2 650 V 0.33 Ω 12 A Extremely low gate charge Excellent output capacitance (Coss) profile 100% avalanche tested Zener-protected Applications TO-220FP ultra narrow leads Figure 1: Internal schematic diagram D(2)   Switching applications LLC converters, resonant converters Description This device is an N-channel Power MOSFET developed using MDmesh™ M2 technology. Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance and optimized switching characteristics, rendering it suitable for the most demanding high efficiency converters. G(1) S(3) AM15572v1_no_tab Table 1: Device summary Order code Marking Package Packaging STFU18N65M2 18N65M2 TO-220FP ultra narrow leads Tube October 2015 DocID027562 Rev 2 This is information on a product in full production. 1/12 www.st.com Contents STFU18N65M2 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuit ....................................................................................... 8 4 Package mechanical data ............................................................... 9 4.1 5 2/12 TO-220FP unl package information .................................................. 9 Revision history ............................................................................ 11 DocID027562 Rev 2 STFU18N65M2 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter VGS ID Value Unit Gate-source voltage ± 25 V Drain current (continuous) at TC = 25 °C 12(1) A A Drain current (continuous) at TC = 100 °C 8(1) IDM(2) Drain current (pulsed) 48(1) A PTOT Total dissipation at TC = 25 °C 25 W VISO Insulation withstand voltage (RMS) from all three leads to external heat sink (t = 1 s; TC = 25 °C) 2500 V ID dv/dt (3) Peak diode recovery voltage slope 15 dv/dt (4) MOSFET dv/dt ruggedness 50 Tstg Storage temperature Tj V/ns - 55 to 150 Max. operating junction temperature °C Notes: (1)Limited (2)Pulse (3)I SD (4)V by maximum junction temperature. width limited by safe operating area. ≤ 10 A, di/dt ≤ 400 A/µs; VDSpeak < V(BR)DSS, VDD = 400 V DS ≤ 520 V Table 3: Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case max Rthj-amb Thermal resistance junction-ambient max Value Unit 5 °C/W 62.5 °C/W Table 4: Avalanche characteristics Symbol Parameter Value Unit IAR Avalanche current, repetitive or not repetitive (pulse width limited by T jmax) 2 A EAS Single pulse avalanche energy (starting Tj = 25°C, ID = IAR; VDD = 50 V) 450 mJ DocID027562 Rev 2 3/12 Electrical characteristics 2 STFU18N65M2 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 5: On /off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage ID = 1 mA, VGS = 0 V Min. Typ. Max. 650 Unit V 1 µA VDS = 650 V, TC = 125 °C 100 µA Gate-body leakage current (VDS = 0) VGS = ± 25 V ±10 µA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 3 4 V RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 6 A 0.275 0.33 Ω Min. Typ. Max. Unit - 770 - pF - 35 - pF - 1.2 - pF pF IDSS Zero gate voltage drain current (VGS = 0) IGSS VDS = 650 V 2 Table 6: Dynamic Symbol Ciss Parameter Test conditions Input capacitance VDS = 100 V, f = 1 MHz, VGS = 0 V Coss Output capacitance Crss Reverse transfer capacitance C (1) oss eq. Equivalent output capacitance VDS = 0 to 520 V, VGS = 0 V - 175 - RG Intrinsic gate resistance f = 1 MHz, ID = 0 - 6.1 - Ω Qg Total gate charge - 20 - nC Qgs Gate-source charge - 3.6 - nC Qgd Gate-drain charge VDD = 520 V, ID = 12 A, VGS = 10 V ( see Figure 15: "Test circuit for gate charge behavior" ) - 8.5 - nC Notes: (1)C oss eq. is defined as a constant equivalent capacitance giving the same charging time as C oss when VDS increases from 0 to 80% VDSS. Table 7: Switching times Symbol td(on) tr td(off) tf 4/12 Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions Min. Typ. Max. Unit VDD = 325 V, ID = 6 A, RG = 4.7 Ω, VGS = 10 V ( see Figure 14: "Test circuit for resistive load switching times" and Figure 19: "Switching time waveform" ) - 11 - ns - 7.5 - ns - 46 - ns - 12.5 - ns DocID027562 Rev 2 STFU18N65M2 Electrical characteristics Table 8: Source drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit ISD Source-drain current - 12 A ISDM(1) Source-drain current (pulsed) - 48 A VSD(2) Forward on voltage - 1.6 V ISD = 12 A, VGS = 0 V trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ISD = 12 A, di/dt = 100 A/µs, VDD = 60 V ( see Figure 16: "Test circuit for inductive load switching and diode recovery times" ) ISD = 12 A, di/dt = 100 A/µs, VDD = 60 V, Tj = 150 °C, (see Figure 16: "Test circuit for inductive load switching and diode recovery times" ) - 331 ns - 3.4 µC - 20.5 A - 462 ns - 4.6 µC - 20 A Notes: (1)Pulse width limited by safe operating area. (2)Pulsed: pulse duration = 300 µs, duty cycle 1.5%. DocID027562 Rev 2 5/12 Electrical characteristics 2.1 STFU18N65M2 Electrical characteristics (curves) Figure 3: Thermal impedance Figure 2: Safe operating area ID(A) GIPG070120151641FSR 1 0.1 0.1 n) 10µs DS (o Op Lim era ite tion d by in th m is ax ar R ea is 10 100 µs Tj=150°C Tc=25°C Single pulse 1 10 1ms 10ms V DS (V) 100 Figure 4: Output characteristics ID(A) Figure 5: Transfer characteristics GIPG161220141431ALS V GS = 6,7,8,9,10 V 25 25 V GS = 5 V 20 20 15 15 10 10 V GS = 4 V 5 0 GIPG161220141436ALS ID (A) V DS = 16 v 5 0 8 4 0 12 16 V DS (V) Figure 6: Gate charge vs gate-source voltage V GS (V) GIPG161220141455ALSV DS 12 V DS = 520V ID = 12 A 10 4 R DS(on) (Ω) 600 0.290 0.285 VGS = 10 V 0.280 6 300 4 200 2 100 0.270 0 Qg(nC) 0.265 0 0 6/12 4 8 12 16 20 V GS (V) GIPG161220141505ALS 400 8 8 6 Figure 7: Static drain-source on-resistance (V) 500 2 0 0.275 DocID027562 Rev 2 0 2 4 6 8 10 12 ID(A) STFU18N65M2 Electrical characteristics Figure 8: Capacitance variations C (pF) Figure 9: Output capacitance stored energy GIPG161220141520ALS E OSS (µJ) GIPG161220141616ALS 6 1000 C iss 5 4 100 3 C oss 2 10 1 1 0.1 1 10 C rss V DS (V) 100 Figure 10: Normalized gate threshold voltage vs temperature GIPG161220141528ALS V GS(th) (norm) 0 100 200 300 400 500 600 V DS (V) Figure 11: Normalized on-resistance vs temperature GIPG161220141538ALS R DS(on) (norm) 2.2 ID = 250 µ A 1.1 0 1.8 1.0 V GS = 10 V 1.4 0.9 1.0 0.8 0.6 0.7 0.6 -75 25 -25 75 125 T J(°C) Figure 12: Source-drain diode forward characteristics V SD (V) GIPG121620141553ALS 0.2 -75 -25 25 75 125 T J(°C) Figure 13: Normalized V(BR)DSS vs temperature V (BR)DSS (norm) GIPG121620141601ALS 1.08 1.2 T J=-50°C 1.04 ID = 1 m A 1.0 1.00 T J=25°C 0.8 0.96 T J=150°C 0.6 0.92 0.4 0.88 -75 0 2 4 6 8 10 12 ISD (A) DocID027562 Rev 2 -25 25 75 125 T J(°C) 7/12 Test circuit 3 STFU18N65M2 Test circuit Figure 15: Test circuit for gate charge behavior Figure 14: Test circuit for resistive load switching times Figure 16: Test circuit for inductive load switching and diode recovery times Figure 17: Unclamped inductive load test circuit Figure 18: Unclamped inductive waveform 8/12 DocID027562 Rev 2 Figure 19: Switching time waveform STFU18N65M2 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 4.1 TO-220FP unl package information Figure 20: TO-220FP ultra narrow leads package outline 8576148_1 DocID027562 Rev 2 9/12 Package mechanical data STFU18N65M2 Table 9: TO-220FP ultra narrow leads mechanical data mm Dim. Min. 10/12 Typ. Max. A 4.40 4.60 B 2.50 2.70 D 2.50 2.75 E 0.45 0.60 F 0.65 0.75 F1 - 0.90 G 4.95 5.20 G1 2.40 H 10.00 10.40 L2 15.10 15.90 L3 28.50 30.50 L4 10.20 11.00 L5 2.50 3.10 L6 15.60 16.40 L7 9.00 9.30 L8 L9 3.20 3.60 - 1.30 Dia. 3.00 3.20 DocID027562 Rev 2 2.54 2.70 STFU18N65M2 5 Revision history Revision history Table 10: Document revision history Date Revision Changes 05-Mar-2015 1 Initial release 07-Oct-2015 2 Document status promoted from preliminary to production data. DocID027562 Rev 2 11/12 STFU18N65M2 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved 12/12 DocID027562 Rev 2