STFU23N80K5

STFU23N80K5 N-channel 800 V, 0.23 Ω typ., 16 A MDmesh™ K5 Power MOSFET in a TO-220FP ultra narrow leads package Datasheet - production data Features 1 2 Order code VDS RDS(on) max. ID PTOT STFU23N80K5 800 V 0.28 Ω 16 A 35 W      3 TO-220FP ultra narrow leads Industry’s lowest RDS(on) x area Industry’s best FoM (figure of merit) Ultra-low gate charge 100% avalanche tested Zener-protected Applications Figure 1: Internal schematic diagram  Switching applications Description This very high voltage N-channel Power MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency. Table 1: Device summary Order code Marking Package Packing STFU23N80K5 23N80K5 TO-220FP ultra narrow leads Tube February 2017 DocID030365 Rev 1 This is information on a product in full production. 1/12 www.st.com Contents STFU23N80K5 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package information ....................................................................... 9 4.1 5 2/12 TO-220FP ultra narrow leads package information ........................... 9 Revision history ............................................................................ 11 DocID030365 Rev 1 STFU23N80K5 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Value Unit Gate-source voltage ±30 V Drain current (continuous) at Tcase = 25 °C 16 Drain current (continuous) at Tcase = 100 °C 10 IDM(1) Drain current (pulsed) 64 A PTOT W VGS ID Parameter Total dissipation at Tcase = 25 °C 35 dv/dt(2) Peak diode recovery voltage slope 4.5 dv/dt(3) MOSFET dv/dt ruggedness 50 VISO Insulation withstand voltage (RMS) from all three leads to external heat sink (t= 1 s, TC= 25 °C) Tstg Storage temperature range Tj Operating junction temperature range A V/ns 2500 V -55 to 150 °C Value Unit Notes: (1)Pulse (2)I SD (3)V width is limited by safe operating area. ≤ 16 A, di/dt=100 A/μs, VDS peak < V(BR)DSS, VDD = 80% V(BR)DSS DS ≤ 640 V Table 3: Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case 3.6 Rthj-amb Thermal resistance junction-ambient 50 °C/W Table 4: Avalanche characteristics Symbol Parameter IAR(1) Avalanche current, repetitive or not repetitive EAS(2) Single pulse avalanche energy Value Unit 5 A 400 mJ Notes: (1)Pulse width limited by Tjmax. (2)Starting Tj = 25 °C, ID = IAR, VDD = 50 V. DocID030365 Rev 1 3/12 Electrical characteristics 2 STFU23N80K5 Electrical characteristics (Tcase = 25 °C unless otherwise specified) Table 5: Static Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage VGS = 0 V, ID = 1 mA Min. Typ. Max. Unit 800 V VGS = 0 V, VDS = 800 V 1 VGS = 0 V, VDS = 800 V, Tcase = 125 °C(1) 50 Gate-body leakage current VDS = 0 V, VGS = ±20 V ±10 µA VGS(th) Gate threshold voltage VDS = VGS, ID = 100 µA 4 5 V RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 8 A 0.23 0.28 Ω Min. Typ. Max. Unit - 1000 - - 65 - - 1.5 - IDSS Zero gate voltage drain current IGSS 3 µA Notes: (1)Defined by design, not subject to production test. Table 6: Dynamic Symbol Ciss Parameter Test conditions Input capacitance VDS = 100 V, f = 1 MHz, VGS = 0 V Coss Output capacitance Crss Reverse transfer capacitance (1) Equivalent output capacitance VDS = 0 to 640 V, VGS = 0 V - 165 - CO(er)(2) Equivalent output capacitance VDS = 0 to 640 V, VGS = 0 V - 59 - RG Intrinsic gate resistance f = 1 MHz, ID = 0 A - 4.7 - VDD = 640 V, ID = 16 A, VGS = 0 to 10 V (see Figure 14: "Test circuit for gate charge behavior") - 33 - - 6 - - 25 - CO(tr) Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge pF pF Ω nC Notes: (1)Time related is defined as a constant equivalent capacitance giving the same charging time as COSS when VDS increases from 0 to 80% VDSS. (2)Energy related is defined as a constant equivalent capacitance giving the same stored energy as C OSS when VDS increases from 0 to 80% VDSS. 4/12 DocID030365 Rev 1 STFU23N80K5 Electrical characteristics Table 7: Switching times Symbol td(on) tr td(off) tf Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions Min. Typ. Max. Unit VDD = 400 V, ID = 8 A RG = 4.7 Ω, VGS = 10 V (see Figure 13: "Test circuit for resistive load switching times" and Figure 18: "Switching time waveform") - 14 - - 9 - - 48 - - 9 - Min. Typ. Max. Unit ns Table 8: Source-drain diode Symbol Parameter Test conditions ISD Source-drain current - 16 A ISDM(1) Source-drain current (pulsed) - 64 A VSD(2) Forward on voltage VGS = 0 V, ISD = 16 A - 1.5 V ISD = 16 A, di/dt = 100 A/µs, VDD = 60 V (see Figure 15: "Test circuit for inductive load switching and diode recovery times") - 410 ns - 7 µC - 34 A ISD = 16 A, di/dt = 100 A/µs, VDD = 60 V, Tj = 150 °C (see Figure 15: "Test circuit for inductive load switching and diode recovery times") - 650 ns - 10 µC - 32 A Min. Typ. Max. Unit ±30 - - V trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current Notes: (1) Pulse width is limited by safe operating area. (2) Pulse test: pulse duration = 300 µs, duty cycle 1.5%. Table 9: Gate-source Zener diode Symbol V(BR)GSO Parameter Gate-source breakdown voltage Test conditions IGS = ±1 mA, ID = 0 A The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection, thus eliminating the need for additional external componentry. DocID030365 Rev 1 5/12 Electrical characteristics 2.1 STFU23N80K5 Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance 6/12 DocID030365 Rev 1 STFU23N80K5 Electrical characteristics Figure 8: Capacitance variations Figure 9: Normalized gate threshold voltage vs temperature Figure 10: Normalized on-resistance vs temperature Figure 11: Normalized V(BR)DSS vs temperature Figure 12: Maximum avalanche energy vs temperature DocID030365 Rev 1 7/12 Test circuits 3 8/12 STFU23N80K5 Test circuits Figure 13: Test circuit for resistive load switching times Figure 14: Test circuit for gate charge behavior Figure 15: Test circuit for inductive load switching and diode recovery times Figure 16: Unclamped inductive load test circuit Figure 17: Unclamped inductive waveform Figure 18: Switching time waveform DocID030365 Rev 1 STFU23N80K5 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 4.1 TO-220FP ultra narrow leads package information Figure 19: TO-220FP ultra narrow leads package outline 8576148_1 DocID030365 Rev 1 9/12 Package information STFU23N80K5 Table 10: TO-220FP ultra narrow leads mechanical data mm Dim. Min. 10/12 Typ. Max. A 4.40 4.60 B 2.50 2.70 D 2.50 2.75 E 0.45 0.60 F 0.65 0.75 F1 - 0.90 G 4.95 5.20 G1 2.40 H 10.00 10.40 L2 15.10 15.90 L3 28.50 30.50 L4 10.20 11.00 L5 2.50 3.10 L6 15.60 16.40 L7 9.00 9.30 L8 L9 3.20 3.60 - 1.30 Dia. 3.00 3.20 DocID030365 Rev 1 2.54 2.70 STFU23N80K5 5 Revision history Revision history Table 11: Document revision history Date Revision 21-Feb-2017 1 Changes First release DocID030365 Rev 1 11/12 STFU23N80K5 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2017 STMicroelectronics – All rights reserved 12/12 DocID030365 Rev 1