STFU24N60M2

STFU24N60M2 N-channel 600 V, 0.168 Ω typ., 18 A MDmesh™ M2 Power MOSFET in a TO-220FP ultra narrow leads package Datasheet - production data Features 1 2      3 TO-220FP ultra narrow leads Order code VDS RDS(on) max ID STFU24N60M2 600 V 0.19 Ω 18 A Extremely low gate charge Lower RDS(on) x area vs previous generation Low gate input resistance 100% avalanche tested Zener-protected Applications Figure 1: Internal schematic diagram D(2)   Switching applications LLC converters, resonant converters Description This device is an N-channel Power MOSFET developed using MDmesh™ M2 technology. Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance and optimized switching characteristics, rendering it suitable for the most demanding high efficiency converters. G(1) S(3) AM15572v1_no_tab Table 1: Device summary Order code Marking Package Packing STFU24N60M2 24N60M2 TO-220FP ultra narrow leads Tube September 2015 DocID027630 Rev 2 This is information on a product in full production. 1/12 www.st.com Contents STFU24N60M2 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuit ....................................................................................... 8 4 Package information ....................................................................... 9 4.1 5 2/12 TO-220FP package information ........................................................ 9 Revision history ............................................................................ 11 DocID027630 Rev 2 STFU24N60M2 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol VGS ID Parameter Value Unit Gate-source voltage ± 25 V Drain current (continuous) at TC = 25 °C 18(1) A A Drain current (continuous) at TC = 100 °C 12(1) IDM(2) Drain current (pulsed) 72(1) A PTOT Total dissipation at TC = 25 °C 30 W VISO Insulation withstand voltage (RMS) from all three leads to external heat sink (t = 1 s; TC = 25 °C) 2500 V ID dv/dt (3) Peak diode recovery voltage slope 15 dv/dt (4) MOSFET dv/dt ruggedness 50 Tstg Storage temperature Tj Max. operating junction temperature - 55 to 150 V/ns °C Notes: (1)Limited (2)Pulse (3)I SD (4)V by maximum junction temperature. width limited by safe operating area. ≤ 18 A, di/dt ≤ 400 A/µs; VDSpeak < V(BR)DSS, VDD = 400 V. DS ≤ 480 V. Table 3: Thermal data Symbol Parameter Value Rthj-case Thermal resistance junction-case max 4.2 Rthj-amb Thermal resistance junction-ambient max 62.5 Unit °C/W Table 4: Avalanche characteristics Symbol Parameter Value Unit IAR Avalanche current, repetitive or not repetitive (pulse width limited by Tjmax) 3.5 A EAS Single pulse avalanche energy (starting Tj = 25°C, ID = IAR; VDD = 50 V) 180 mJ DocID027630 Rev 2 3/12 Electrical characteristics 2 STFU24N60M2 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 5: On /off states Symbol Parameter Test conditions V(BR)DSS Drain-source breakdown voltage ID = 1 mA, VGS = 0 V Min. Typ. Max. 600 Unit V 1 µA VDS = 600 V, TC = 125 °C 100 µA Gate-body leakage current (VDS = 0) VGS = ± 25 V ±10 µA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 3 4 V RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 9 A 0.168 0.19 Ω Min. Typ. Max. Unit - 1060 - pF - 55 - pF - 2.2 - pF IDSS Zero gate voltage drain current (VGS = 0) IGSS VDS = 600 V 2 Table 6: Dynamic Symbol Parameter Test conditions Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Coss eq.(1) Equivalent output capacitance VDS = 0 to 480 V, VGS = 0 V - 258 - pF RG Intrinsic gate resistance f = 1 MHz, ID = 0 - 7 - Ω Qg Total gate charge - 29 - nC Qgs Gate-source charge - 6 - nC Qgd Gate-drain charge VDD = 480 V, ID = 18 A, VGS = 10 V ( see Figure 15: "Test circuit for gate charge behavior" ) - 12 - nC VDS = 100 V, f = 1 MHz, VGS = 0 V Notes: (1)C oss eq. is defined as a constant equivalent capacitance giving the same charging time as C oss when VDS increases from 0 to 80% VDSS. Table 7: Switching times Symbol td(on) tr td(off) tf 4/12 Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions Min. Typ. Max. Unit VDD = 300 V, ID = 9 A, RG = 4.7 Ω, VGS = 10 V ( see Figure 14: "Test circuit for resistive load switching times" and Figure 19: "Switching time waveform" ) - 14 - ns - 9 - ns - 60 - ns - 15 - ns DocID027630 Rev 2 STFU24N60M2 Electrical characteristics Table 8: Source drain diode Symbol Parameter Test conditions ISD(1) Source-drain current ISDM(1)(2) Source-drain current (pulsed) VSD(3) Forward on voltage trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current Min. Typ. Max. Unit - 18 A - 72 A ISD = 18 A, VGS = 0 V - 1.6 V ISD = 18 A, di/dt = 100 A/µs, VDD = 60 V ( see Figure 16: "Test circuit for inductive load switching and diode recovery times" ) - 332 ns - 4 µC - 24 A ISD = 18 A, di/dt = 100 A/µs, VDD = 60 V, Tj = 150 °C, (see Figure 16: "Test circuit for inductive load switching and diode recovery times" ) - 450 ns - 5.5 µC - 25 A Notes: (1)The value is rated according to Rthj-case and limited by package. (2)Pulse width limited by safe operating area. (3)Pulsed: pulse duration = 300 µs, duty cycle 1.5%. DocID027630 Rev 2 5/12 Electrical characteristics 2.1 STFU24N60M2 Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance W 6/12 DocID027630 Rev 2 STFU24N60M2 Electrical characteristics Figure 8: Capacitance variations AM15665v1 C (pF) Figure 9: Normalized gate threshold voltage vs. temperature Ciss 1000 100 Coss 10 Crss 1 0.1 1 10 100 V DS(V) Figure 10: Normalized on-resistance vs temperature Figure 11: Source-drain diode forward characteristics Figure 12: Normalized V(BR)DSS vs temperature Figure 13: Output capacitance stored energy DocID027630 Rev 2 7/12 Test circuit 3 8/12 STFU24N60M2 Test circuit Figure 14: Test circuit for resistive load switching times Figure 15: Test circuit for gate charge behavior Figure 16: Test circuit for inductive load switching and diode recovery times Figure 17: Unclamped inductive load test circuit Figure 18: Unclamped inductive waveform Figure 19: Switching time waveform DocID027630 Rev 2 STFU24N60M2 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 4.1 TO-220FP package information Figure 20: TO-220FP ultra narrow leads package outline 8576148_1 DocID027630 Rev 2 9/12 Package information STFU24N60M2 Table 9: TO-220FP ultra narrow leads mechanical data mm Dim. Min. 10/12 Typ. Max. A 4.40 4.60 B 2.50 2.70 D 2.50 2.75 E 0.45 0.60 F 0.65 0.75 F1 - 0.90 G 4.95 5.20 G1 2.40 H 10.00 10.40 L2 15.10 15.90 L3 28.50 30.50 L4 10.20 11.00 L5 2.50 3.10 L6 15.60 16.40 L7 9.00 9.30 L8 L9 3.20 3.60 - 1.30 Dia. 3.00 3.20 DocID027630 Rev 2 2.54 2.70 STFU24N60M2 5 Revision history Revision history Table 10: Document revision history Date Revision Changes 12-Mar-2015 1 Initial release 08-Sepr-2015 2 Datasheet status promoted from preliminary to production data DocID027630 Rev 2 11/12 STFU24N60M2 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved 12/12 DocID027630 Rev 2