STFU9N65M2

STFU9N65M2 Datasheet N-channel 650 V, 0.79 Ω typ., 5 A MDmesh M2 Power MOSFET in a TO-220FP ultra narrow leads package Features 1 2 3 TO-220FP ultra narrow leads Order code VDS RDS(on) max. ID STFU9N65M2 650 V 0.90 Ω 5A • • Extremely low gate charge Excellent output capacitance (COSS) profile • • 100% avalanche tested Zener-protected D(2) Applications • G(1) Switching applications Description S(3) AM15572v1_no_tab This device is an N-channel Power MOSFET developed using MDmesh M2 technology. Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance and optimized switching characteristics, rendering it suitable for the most demanding high efficiency converters. Product status link STFU9N65M2 Product summary Order code STFU9N65M2 Marking 9N65M2 Package TO-220FP ultra narrow leads Packing Tube DS11781 - Rev 3 - June 2019 For further information contact your local STMicroelectronics sales office. www.st.com STFU9N65M2 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Parameter Value Unit ±25 V VGS Gate-source voltage ID (1) Drain current (continuous) at TC = 25 °C 5 A ID (1) Drain current (continuous) at TC = 100 °C 3.2 A IDM (2) Drain current pulsed 20 A PTOT Total power dissipation at TC = 25 °C 20 W 2.5 kV VISO dv/dt (3) dv/dt (4) TJ Tstg Insulation withstand voltage (RMS) from all three leads to external heat sink (t = 1 s; TC = 25 °C) Peak diode recovery voltage slope 15 MOSFET dv/dt ruggedness 50 Operating junction temperature range Storage temperature range V/ns -55 to 150 °C Value Unit 1. Current limited by package. 2. Pulse width limited by safe operating area. 3. ISD ≤ 5 A, di/dt ≤ 400 A/μs, VDS(peak) ≤ V(BR)DSS, VDD = 400 V. 4. VDS ≤ 520 V. Table 2. Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case 6.25 °C/W Rthj-amb Thermal resistance junction-ambient 62.5 °C/W Value Unit 1 A 105 mJ Table 3. Avalanche characteristics Symbol DS11781 - Rev 3 Parameter IAR Avalanche current, repetitive or not repetitive (pulse width limited by TJ max) EAS Single pulse avalanche energy (starting TJ = 25 °C, ID = IAR, VDD = 50 V) page 2/12 STFU9N65M2 Electrical characteristics 2 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 4. On/off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage Min. VGS = 0 V, ID = 1 mA Typ. 650 Zero gate voltage drain current IGSS Gate-body leakage current VDS = 0 V, VGS = ±25 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 2.5 A VGS = 0 V, VDS = 650 V, TC = 125 Unit V VGS = 0 V, VDS = 650 V IDSS Max. 1 µA 100 µA ±10 µA 3 4 V 0.79 0.90 Ω Min. Typ. Max. Unit - 310 - pF - 18 - pF - 0.9 - pF °C(1) 2 1. Defined by design, not subject to production test. Table 5. Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Test conditions VDS = 100 V, f = 1 MHz, VGS = 0 V Equivalent capacitance energy related VDS = 0 to 520 V, VGS = 0 V - 109 - pF Rg Intrinsic gate resistance f = 1 MHz open drain - 6.6 - Ω Qg Total gate charge VDD = 520 V, ID = 5 A - 10.3 - nC Gate-source charge VGS = 0 to 10 V - 2.4 - nC Gate-drain charge (see Figure 14. Test circuit for gate charge behavior) - 4.8 - nC Coss eq. (1) Qgs Qgd 1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. Table 6. Switching times Symbol td(on) tr td(off) tf DS11781 - Rev 3 Parameter Test conditions Min. Typ. Max. Unit Turn-on delay time VDD = 325 V, ID = 2.5 A, - 7.5 - ns Rise time RG = 4.7 Ω, VGS = 10 V - 6.6 - ns Turn-off delay time (see Figure 13. Test circuit for resistive load switching times and Figure 18. Switching time waveform) - 22.5 - ns - 18 - ns Fall time page 3/12 STFU9N65M2 Electrical characteristics Table 7. Source-drain diode Symbol ISD Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 5 A ISDM (1) Source-drain current (pulsed) - 20 A VSD (2) Forward on voltage ISD = 5 A, VGS = 0 V - 1.6 V trr Reverse recovery time ISD = 5 A, VDD = 60 V - 276 ns Qrr Reverse recovery charge di/dt = 100 A/µs - 1.7 µC Reverse recovery current (see Figure 15. Test circuit for inductive load switching and diode recovery times) - 12.5 A Reverse recovery time ISD = 5 A, VDD = 60 V - 312 ns Reverse recovery charge di/dt = 100 A/µs, - 1.9 µC - 12.4 A IRRM trr Qrr TJ = 150 °C IRRM Reverse recovery current (see Figure 15. Test circuit for inductive load switching and diode recovery times) 1. Pulse width limited by safe operating area. 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5 %. DS11781 - Rev 3 page 4/12 STFU9N65M2 Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Figure 1. Safe operating area Figure 2. Thermal Impedance AM18056v1 ID (A) K GC20940 on ) 10µs S( O p Li era m ite tion d by in t m his ax a RD rea is 10 1 10 -1 100µs 1ms 10ms 0.1 10 -2 Tj=150°C Tc=25°C Single pulse 0.01 0.1 1 10 VDS(V) 100 10 -3 10 -4 Figure 3. Output characteristics ID (A) ID (A) GADG160320171044OCH VGS = 7 V 8 6 4 4 8 12 16 20 VDS (V) Figure 5. Gate charge vs gate-source voltage VGS (V) GADG160320171046QVG VDS (V) VDD = 520 V, ID = 5 A 12 600 0 0 2 4 6 8 VGS (V) Figure 6. Static drain-source on-resistance AM18062v1 RDS(on) (Ω) 0.840 VGS=10V 0.830 10 500 VDS 8 VDS = 20 V 2 VGS = 5 V 4 t p (s) 10 0 GADG160320171044TCH 8 6 0 0 10 -1 10 VGS = 6 V 2 10 -2 Figure 4. Transfer characteristics VGS = 8, 9, 10 V 10 10 -3 400 6 300 0.820 0.810 0.800 0.790 4 200 2 100 0.770 0 Qg (nC) 0.760 0 0 DS11781 - Rev 3 2 4 6 8 10 0.780 0 1 2 3 4 5 ID(A) page 5/12 STFU9N65M2 Electrical characteristics (curves) Figure 7. Capacitance variations C (pF) Figure 8. Output capacitance stored energy EOSS GADG160320171212CVR 2.5 10 3 CISS 10 2 10 1 GADG160320171046EOS 2.0 1.5 COSS 1.0 10 0 10 -1 10 -1 f = 1 MHz CRSS 10 0 10 1 10 2 VDS (V) Figure 9. Normalized gate threshold voltage vs temperature VGS(th) (norm.) GADG160320171045VTH 0.0 0 100 200 300 400 500 600 VDS (V) Figure 10. Normalized on-resistance vs temperature RDS(on) (norm.) GADG160320171045RON 2.2 1.1 ID = 250 µA 1.8 1.0 VGS = 10 V 1.4 0.9 1.0 0.8 0.6 0.7 0.6 -75 0.5 -25 25 75 125 Tj (°C) Figure 11. Normalized V(BR)DSS vs temperature V(BR)DSS (norm.) GADG160320171046BDV 1.12 0.2 -75 -25 25 ID = 1 mA Tj (°C) AM18068v1 VSD (V) TJ=-50°C 0.9 1.04 125 Figure 12. Source-drain diode forward characteristics 1 1.08 75 TJ=25°C 0.8 1.00 0.7 0.96 TJ=150°C 0.6 0.92 0.88 -75 DS11781 - Rev 3 0.5 -25 25 75 125 Tj (°C) 1 2 3 4 ISD(A) page 6/12 STFU9N65M2 Test circuits 3 Test circuits Figure 13. Test circuit for resistive load switching times Figure 14. Test circuit for gate charge behavior VDD 12 V 2200 + μF 3.3 μF VDD VD VGS 1 kΩ 100 nF RL IG= CONST VGS RG 47 kΩ + pulse width D.U.T. 2.7 kΩ 2200 μF pulse width D.U.T. 100 Ω VG 47 kΩ 1 kΩ AM01469v1 AM01468v1 Figure 15. Test circuit for inductive load switching and diode recovery times D G A D.U.T. S 25 Ω A L A B B 3.3 µF D G + VD 100 µH fast diode B Figure 16. Unclamped inductive load test circuit RG 1000 + µF 2200 + µF VDD 3.3 µF VDD ID D.U.T. S D.U.T. Vi _ pulse width AM01471v1 AM01470v1 Figure 18. Switching time waveform Figure 17. Unclamped inductive waveform ton V(BR)DSS td(on) VD toff td(off) tr tf 90% 90% IDM VDD 10% 0 ID VDD AM01472v1 VGS 0 VDS 10% 90% 10% AM01473v1 DS11781 - Rev 3 page 7/12 STFU9N65M2 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 4.1 TO-220FP ultra narrow leads package information Figure 19. TO-220FP ultra narrow leads package outline DS11781 - Rev 3 page 8/12 STFU9N65M2 TO-220FP ultra narrow leads package information Table 8. TO-220FP ultra narrow leads mechanical data Dim. DS11781 - Rev 3 mm Min. Typ. Max. A 4.40 4.60 B 2.50 2.70 D 2.50 2.75 E 0.45 0.60 F 0.65 0.75 F1 - 0.90 G 4.95 5.20 G1 2.40 H 10.00 10.40 L2 15.10 15.90 L3 28.50 30.50 L4 10.20 11.00 L5 2.50 3.10 L6 15.60 16.40 L7 9.00 9.30 L8 3.20 3.60 L9 - 1.30 Dia. 3.00 3.20 2.54 2.70 page 9/12 STFU9N65M2 Revision history Table 9. Document revision history Date Revision Changes 04-Aug-2016 1 First release. 08-Sep-2016 2 Document status updated from preliminary to production data. Updated Table 1. Absolute maximum ratings and Table 5. Dynamic. 21-Jun-2019 3 Updated Section 2.1 Electrical characteristics (curves). Minor text changes. DS11781 - Rev 3 page 10/12 STFU9N65M2 Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4.1 TO-220FP ultra narrow leads package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 DS11781 - Rev 3 page 11/12 STFU9N65M2 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2019 STMicroelectronics – All rights reserved DS11781 - Rev 3 page 12/12