STFW2N105K5

STFW2N105K5 N-channel 1050 V, 6 Ω typ., 1.5 A Zener-protected SuperMESH™ 5 Power MOSFET in a TO-3PF package Datasheet - preliminary data Features Order code VDS RDS(on) max STFW2N105K5 1050 V 1 8Ω ID PTOT 1.5 A 30 W • Worldwide best FOM (figure of merit) • Ultra low gate charge 3 • 100% avalanche tested 2 1 • Zener-protected TO-3PF Applications • Switching applications Figure 1. Internal schematic diagram Description ' This N-channel Zener-protected Power MOSFET is designed using ST’s revolutionary avalancherugged very high voltage SuperMESH™ 5 technology, based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance, and ultra-low gate charge for applications which require superior power density and high efficiency. * 6 AM01476v1 Table 1. Device summary Order code Marking Package Packaging STFW2N105K5 2N105K5 TO-3PF Tube May 2014 DocID026320 Rev 1 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/14 www.st.com Contents STFW2N105K5 Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Test circuits 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2/14 .............................................. 9 DocID026320 Rev 1 STFW2N105K5 1 Electrical ratings Electrical ratings Table 2. Absolute maximum ratings Symbol VGS ID ID IDM Parameter Gate- source voltage Drain current (continuous) at TC = 25 °C Drain current (continuous) at TC = 100 °C Value Unit 30 V (1) A 2 1.3 (1) A Drain current (pulsed) 6 A Total dissipation at TC = 25 °C 30 W IAR Max current during repetitive or single pulse avalanche 0.5 A EAS Single pulse avalanche energy (starting TJ = 25 °C, ID=IAS, VDD= 50 V) 90 mJ dv/dt (2) Peak diode recovery voltage slope 4.5 V/ns dv/dt(3) MOSFET dv/dt ruggedness 50 V/ns 3500 V -55 to 150 °C Value Unit PTOT VISO Insulation withstand voltage (RMS) from all three leads to external heat sink (t=1 s; TC=25 °C) Tj Tstg Operating junction temperature Storage temperature 1. Pulse width limited by safe operating area. 2. ISD ≤ 1.5 A, di/dt ≤ 100 A/μs, VPeak ≤ V(BR)DSS. 3. VSD ≤ 840 V Table 3. Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case max 4.2 °C/W Rthj-amb Thermal resistance junction-ambient max 50 °C/W DocID026320 Rev 1 3/14 14 Electrical characteristics 2 STFW2N105K5 Electrical characteristics (Tcase =25 °C unless otherwise specified) Table 4. On /off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage ID = 1 mA, VGS = 0 Min. Typ. Max. Unit 1050 V VDS = 1050 V 1 μA VDS = 1050 V, TC=125 °C 50 μA Gate-body leakage current VGS = ± 20 V; VDS=0 10 μA VGS(th) Gate threshold voltage VDS = VGS, ID = 100 μA 4 5 V RDS(on) Static drain-source onresistance VGS = 10 V, ID = 0.75 A 6 8 Ω IDSS IGSS Zero gate voltage, drain current (VGS = 0) 3 Table 5. Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit - 115 - pF - 15 - pF Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance - 0.5 - pF Co(tr)(1) Equivalent capacitance time related - 17 - pF Co(er)(2) Equivalent capacitance energy related - 6 - pF RG Intrinsic gate resistance f = 1 MHz open drain - 20 - Ω Qg Total gate charge - 10 - nC Qgs Gate-source charge - 1.5 - nC Qgd Gate-drain charge VDD = 840 V, ID = 1.5 A VGS =10 V (see Figure 16) - 8 - nC VDS =100 V, f=1 MHz, VGS=0 VGS = 0, VDS = 0 to 840 V 1. Time related is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS 2. energy related is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS increases from 0 to 80% VDSS 4/14 DocID026320 Rev 1 STFW2N105K5 Electrical characteristics Table 6. Switching times Symbol td(on) tr Parameter Test conditions tf Typ. Max Unit - 14.5 - ns - 8.5 - ns - 35 - ns - 38.5 - ns Min. Typ. Max Unit Turn-on delay time VDD = 525 V, ID = 0.75 A, RG = 4.7 Ω, VGS = 10 V (see Figure 15) Rise time td(off) Min. Turn-off-delay time Fall time Table 7. Source drain diode Symbol ISD ISDM (1) VSD (2) Parameter Test conditions Source-drain current - 1.5 A Source-drain current (pulsed) - 6 A 1.5 V Forward on voltage ISD = 1.5 A, VGS = 0 - trr Reverse recovery time - 326 ns Qrr Reverse recovery charge - 1.19 μC IRRM Reverse recovery current ISD = 1.5 A, di/dt = 100 A/μs VDD= 60 V (see Figure 17) - 7.3 A - 525 ns - 1.83 μC - 7 A trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ISD = 1.5 A, di/dt = 100 A/μs VDD= 60 V TJ = 150 °C (see Figure 17) 1. Pulse width limited by safe operating area 2. Pulsed: pulse duration = 300 μs, duty cycle 1.5% Table 8. Gate-source Zener diode Symbol Parameter Test conditions V(BR)GSO Gate-source breakdown voltage IGS = ± 1mA, ID=0 Min Typ. Max. Unit 30 - - V The built-in back-to-back Zener diodes have specifically been designed to enhance the device's ESD capability. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device's integrity. These integrated Zener diodes thus avoid the usage of external components. DocID026320 Rev 1 5/14 14 Electrical characteristics 2.1 STFW2N105K5 Electrical characteristics (curves) Figure 2. Safe operating area Figure 3. Thermal impedance GIPG210320141515SA ID (A) Zth_TO3PF K δ=0.5 Operation in this area is Limited by max RDS(on) 0.2 1 100μs 0.1 1ms 0.05 -1 10 0.02 10ms 0.1 0.01 Tj=150°C Tc=25°C Single pulse Single pulse -2 0.01 0.1 10 1 100 1000 VDS(V) 10 -5 10 Figure 4. Output characteristics -2 -3 10 10 -1 10 0 10 tp (s) Figure 5. Transfer characteristics GIPG210320141045SA ID (A) -4 10 VGS= 10,11V GIPG210320141056SA ID (A) VDS= 20V 2.5 2.5 9V 2 2.0 8V 1.5 1.5 1.0 1 7V 0.5 0.5 6V 0.0 0 2 4 8 10 12 14 16 6 VDS(V) Figure 6. Gate charge vs gate-source voltage GIPG210320141105SA VDS (V) VGS (V) 6 7 8 9 10 VGS(V) Figure 7. Static drain-source on-resistance GIPG210320141116SA RDS(on) (Ω) VGS= 10V 800 VDD = 840 V ID = 1.5 A 12 0 5 10 700 10 600 8 500 6 400 8 6 300 4 4 200 2 2 0 0 6/14 100 2 4 6 8 10 0 Qg(nC) 0 0 DocID026320 Rev 1 0.2 0.4 0.6 0.8 1.0 1.2 1.4 ID(A) STFW2N105K5 Electrical characteristics Figure 8. Capacitance variations GIPG210320141129SA C (pF) Figure 9. Output capacitance stored energy GIPG210320141201SA E (µJ) 1000 100 2 10 1 0.1 0.1 10 1 VDS(V) 100 Figure 10. Normalized gate threshold voltage vs temperature GIPG210320141203SA VGS(th) (norm) 1.2 0 0 200 400 600 800 VDS(V) Figure 11. Normalized on-resistance vs temperature GIPG210320141419SA RDS(on) (norm) 2.5 ID= 0.75A VGS= 10V 2 1 1.5 0.8 1 0.6 0.5 0.4 -100 -50 0 50 100 150 Tj(°C) Figure 12. Source-drain diode forward characteristics GIPG210320141436SA VSD (V) -50 0 50 100 150 Tj(°C) Figure 13. Normalized V(BR)DSS vs temperature GIPG210320141421SA V(BR)DSS (norm) 1.15 Tj= -50°C 1 0 -100 ID= 1mA 1.1 0.9 1.05 0.8 Tj= 25°C 1 0.7 0.95 Tj= 150°C 0.6 0.5 0.9 0 0.2 0.4 0.6 0.8 1 1.2 ISD(A) 0.85 -100 DocID026320 Rev 1 -50 0 50 100 150 Tj(°C) 7/14 14 Electrical characteristics STFW2N105K5 Figure 14. Maximum avalanche energy vs starting TJ *,3*6$ ($6 P-           8/14         7-ƒ& DocID026320 Rev 1 STFW2N105K5 3 Test circuits Test circuits Figure 15. Switching times test circuit for resistive load Figure 16. Gate charge test circuit VDD 12V 47kΩ 1kΩ 100nF 3.3 μF 2200 RL μF IG=CONST VDD VGS 100Ω Vi=20V=VGMAX VD RG 2200 μF D.U.T. D.U.T. VG 2.7kΩ PW 47kΩ 1kΩ PW AM01468v1 Figure 17. Test circuit for inductive load switching and diode recovery times A A AM01469v1 Figure 18. Unclamped inductive load test circuit L A D G D.U.T. FAST DIODE B B VD L=100μH S 3.3 μF B 25 Ω 1000 μF D VDD 2200 μF 3.3 μF VDD ID G RG S Vi D.U.T. Pw AM01470v1 AM01471v1 Figure 19. Unclamped inductive waveform Figure 20. Switching time waveform ton V(BR)DSS tdon VD toff tr tdoff tf 90% 90% IDM 10% ID VDD 10% 0 VDD VDS 90% VGS AM01472v1 0 DocID026320 Rev 1 10% AM01473v1 9/14 14 Package mechanical data 4 STFW2N105K5 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 10/14 DocID026320 Rev 1 STFW2N105K5 Package mechanical data Figure 21. TO-3PF drawing 7627132_D DocID026320 Rev 1 11/14 14 Package mechanical data STFW2N105K5 Table 9. TO-3PF mechanical data mm Dim. Min. Typ. A 5.30 5.70 C 2.80 3.20 D 3.10 3.50 D1 1.80 2.20 E 0.80 1.10 F 0.65 0.95 F2 1.80 2.20 G 10.30 11.50 G1 12/14 Max. 5.45 H 15.30 15.70 L 9.80 L2 22.80 23.20 L3 26.30 26.70 L4 43.20 44.40 L5 4.30 4.70 L6 24.30 24.70 L7 14.60 15 N 1.80 2.20 R 3.80 4.20 Dia 3.40 3.80 10 DocID026320 Rev 1 10.20 STFW2N105K5 5 Revision history Revision history Table 10. Document revision history Date Revision 08-May-2014 1 Changes First release. DocID026320 Rev 1 13/14 14 STFW2N105K5 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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