STFW8N120K5

STFW8N120K5 Datasheet N-channel 1200 V, 1.65 Ω typ., 6 A, MDmesh K5 Power MOSFET in a TO-3PF package Features 1 2 3 Order code VDS RDS(on) max. ID PTOT STFW8N120K5 1200 V 2.00 Ω 6A 48 W • Industry’s lowest RDS(on) x area • • • • Industry’s best FoM (figure of merit) Ultra-low gate charge 100% avalanche tested Zener-protected Applications TO-3PF • Switching applications D(2) Description This very high voltage N-channel Power MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency. G(1) S(3) AM01476v1_No_tab Product status link STFW8N120K5 Product summary Order code STFW8N120K5 Marking 8N120K5 Package TO-3PF Packing Tube DS12562 - Rev 2 - July 2018 For further information contact your local STMicroelectronics sales office. www.st.com STFW8N120K5 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Value Unit ±30 V Drain current (continuous) at TC = 25 °C 6 A Drain current (continuous) at TC = 100 °C 3.5 A IDM(1) Drain current pulsed 12 A PTOT Total dissipation at TC = 25 °C 48 W VISO Insulation withstand voltage (RMS) from all three leads to external heat sink (t = 1 s, TC = 25 °C) 3.5 kV dv/dt(2) Peak diode recovery voltage slope 4.5 dv/dt(3) MOSFET dv/dt ruggedness 50 VGS ID Tj Tstg Parameter Gate-source voltage Operating junction temperature range Storage temperature range V/ns -55 to 150 °C Value Unit 1. Pulse width limited by safe operating area 2. ISD ≤ 6 A, di/dt ≤ 100 A/μs, VDS peak ≤ V(BR)DSS 3. VDS ≤ 960 V Table 2. Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case 2.6 °C/W Rthj-amb Thermal resistance junction-ambient 50 °C/W Value Unit 1.7 A 415 mJ Table 3. Avalanche characteristics Symbol IAR EAS DS12562 - Rev 2 Parameter Avalanche current, repetitive or not repetitive (pulse width limited by Tjmax) Single-pulse avalanche energy (starting TJ = 25 °C, ID = IAR, VDD = 50 V) page 2/12 STFW8N120K5 Electrical characteristics 2 Electrical characteristics TC = 25 °C unless otherwise specified Table 4. On/off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage VGS = 0 V, ID = 1 mA Min. Typ. 1200 1 µA 50 µA ±10 µA 4 5 V 1.65 2.00 Ω Min. Typ. Max. Unit - 505 - pF - 44 - pF - 0.4 - pF - 70 - pF - 24 - pF VGS = 0 V, VDS = 1200 V Zero gate voltage drain current TC = 125 °C (1) IGSS Gate body leakage current VDS = 0 V, VGS = ±20 V VGS(th) Gate threshold voltage VDS = VGS, ID = 100 µA RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 2.5 A Unit V VGS = 0 V, VDS = 1200 V IDSS Max. 3 1. Defined by design, not subject to production test. Table 5. Dynamic characteristics Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Co(tr)(1) (2) Co(er) Test conditions VDS = 100 V, VGS = 0 V, f = 1 MHz Time-related equivalent capacitance Energy-related equivalent capacitance VDS = 0 to 960 V, VGS = 0 V Rg Intrinsic gate resistance f = 1 MHz , ID = 0 A - 7.7 - Ω Qg Total gate charge VDD = 960 V, ID = 5 A - 13.7 - nC Gate-source charge VGS = 0 to 10 V - 3.6 - nC Gate-drain charge (see Figure 14. Test circuit for gate charge behavior ) - 7.1 - nC Qgs Qgd 1. Co(tr) is a constant capacitance value that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS. 2. Co(er) is a constant capacitance value that gives the same stored energy as Coss while VDS is rising from 0 to 80% VDSS. Table 6. Switching times Symbol td(on) tr td(off) tf DS12562 - Rev 2 Parameter Test conditions Min. Typ. Max. Unit Turn-on delay time VDD = 600 V, ID = 2.5 A, - 15.5 - ns Rise time RG = 4.7 Ω, VGS = 10 V - 11 - ns Turn-off delay time (see Figure 13. Test circuit for resistive load switching times and Figure 18. Switching time waveform) - 40 - ns - 27 - ns Fall time page 3/12 STFW8N120K5 Electrical characteristics Table 7. Source-drain diode Symbol ISD ISDM(1) (2) Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 6 A Source-drain current (pulsed) - 12 A 1.5 V Forward on voltage ISD = 5 A, VGS = 0 V - trr Reverse recovery time ISD = 5 A, VDD = 60 V, - 327 ns Qrr Reverse recovery charge di/dt = 100 A/µs - 3 µC Reverse recovery current (see Figure 15. Test circuit for inductive load switching and diode recovery times) - 18.4 A trr Reverse recovery time ISD = 5 A, VDD = 60 V, - 485 ns Qrr Reverse recovery charge di/dt = 100 A/µs, Tj = 150 °C - 3.9 µC Reverse recovery current (see Figure 15. Test circuit for inductive load switching and diode recovery times) - 16 A Min. Typ. Max Unit ±30 - - V VSD IRRM IRRM 1. Pulse width limited by safe operating area. 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%. Table 8. Gate-source Zener diode Symbol V(BR)GSO Parameter Gate-source breakdown voltage Test conditions IGS = ±1 mA, ID = 0 A The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection, thus eliminating the need for additional external componentry. DS12562 - Rev 2 page 4/12 STFW8N120K5 Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Figure 2. Thermal impedance Figure 1. Safe operating area ID (A) K GIPG200420181209SOA Operation in this area is limited by R DS(on) ZthTO3pf-280umS2 δ=0.5 0.2 tp =10 µs 10 1 10 -1 0.1 tp =100 µs 10 0 10 0.05 tp =1 ms tp =10 ms TJ≤150 °C TC=25 °C VGS=10 V single pulse -1 10 -2 10 -1 10 0 10 1 10 2 Single pulse tp 10 3 VDS (V) 10-3 10-5 10-4 4 8 12 16 VDS (V) GIPG180420180911QVG VDS VDS 16 12 (V) VDD = 960 V ID = 5 A Qg Qgs Qgd 8 4 0 0 DS12562 - Rev 2 4 8 12 16 tp(s) VDS = 20 V 2 Figure 5. Gate charge vs gate-source voltage VGS (V) 101 4 VGS = 6 V 0 0 Ƭ GADG040420181100TCH 6 VGS = 7 V 2 10-1 10-0 8 VGS = 8 V 4 10-2 ID (A) VGS = 9, 10 V 6 10-3 Figure 4. Transfer characteristics GADG040420181101OCH 8 Zth= K*R thj-c δ = tp/T 0.01 Figure 3. Output characteristics ID (A) 0.02 10-2 0 4 5 6 7 8 VGS (V) Figure 6. Static drain-source on-resistance RDS(on) (Ω) 800 1.85 600 1.75 400 1.65 200 1.55 0 Qg (nC) 1.45 0 GADG040420181100RID VGS = 10 V 1 2 3 4 5 ID (A) page 5/12 STFW8N120K5 Electrical characteristics (curves) Figure 8. Normalized gate threshold voltage vs temperature Figure 7. Capacitance variations C (pF) GADG030420180840CVR 10 3 10 VGS(th) (norm.) CISS GADG040420181102VTH 1.2 2 COSS 10 1 CRSS f = 1 MHz 10 0 10 -1 ID = 100 µA 1 0.8 0.6 10 -2 10 -1 10 0 10 1 VDS (V) 10 2 Figure 9. Normalized on-resistance vs temperature RDS(on) (norm.) GADG040420181103RON 0.4 -75 -25 25 75 125 Tj (°C) Figure 10. Normalized V(BR)DSS vs temperature V(BR)DSS (norm.) GADG040420181102BDV 1.12 2.5 1.08 2 ID = 1 mA VGS = 10 V 1.04 1.5 1 1 0.96 0.5 0 -75 0.92 -25 25 75 125 Tj (°C) Figure 11. Source-drain diode forward characteristics VSD (V) GADG040420181103SDF Tj = -50 °C 0.9 0.7 DS12562 - Rev 2 25 75 125 Tj (°C) Figure 12. Maximum avalanche energy vs starting TJ EAS (mJ) GADG040420181104EAS Single pulse, ID = 1.7 A, VDD = 50 V 300 200 Tj = 150 °C 0.6 0.5 0 -25 400 Tj = 25 °C 0.8 0.88 -75 100 1 2 3 4 5 ISD (A) 0 -75 -25 25 75 125 TJ (°C) page 6/12 STFW8N120K5 Test circuits 3 Test circuits Figure 13. Test circuit for resistive load switching times Figure 14. Test circuit for gate charge behavior VDD 12 V 2200 + μF 3.3 μF VDD VD VGS 1 kΩ 100 nF RL IG= CONST VGS RG 47 kΩ + pulse width D.U.T. 2.7 kΩ 2200 μF pulse width D.U.T. 100 Ω VG 47 kΩ 1 kΩ AM01469v1 AM01468v1 Figure 15. Test circuit for inductive load switching and diode recovery times D G A D.U.T. S 25 Ω A L A B B 3.3 µF D G + VD 100 µH fast diode B Figure 16. Unclamped inductive load test circuit RG 1000 + µF 2200 + µF VDD 3.3 µF VDD ID D.U.T. S D.U.T. Vi _ pulse width AM01471v1 AM01470v1 Figure 18. Switching time waveform Figure 17. Unclamped inductive waveform ton V(BR)DSS td(on) VD toff td(off) tr tf 90% 90% IDM VDD 10% 0 ID VDD AM01472v1 VGS 0 VDS 10% 90% 10% AM01473v1 DS12562 - Rev 2 page 7/12 STFW8N120K5 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 4.1 TO-3PF package information Figure 19. TO-3PF package outline 7627132_5 DS12562 - Rev 2 page 8/12 STFW8N120K5 TO-3PF package information Table 9. TO-3PF mechanical data Dim. mm Min. Max. A 5.30 5.70 C 2.80 3.20 D 3.10 3.50 D1 1.80 2.20 E 0.80 1.10 F 0.65 0.95 F2 1.80 2.20 G 10.30 11.50 G1 DS12562 - Rev 2 Typ. 5.45 H 15.30 15.70 L 9.80 L2 22.80 23.20 L3 26.30 26.70 L4 43.20 44.40 L5 4.30 4.70 L6 24.30 24.70 L7 14.60 15 N 1.80 2.20 R 3.80 4.20 Dia 3.40 3.80 10 10.20 page 9/12 STFW8N120K5 Revision history Table 10. Document revision history Date Version 20-Apr-2018 1 Changes Initial release. Document status promoted from preliminary to production data. 02-Jul-2018 2 Updated Figure 2. Thermal impedance. Minor text changes DS12562 - Rev 2 page 10/12 STFW8N120K5 Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4.1 TO-3PF package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 DS12562 - Rev 2 page 11/12 STFW8N120K5 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2018 STMicroelectronics – All rights reserved DS12562 - Rev 2 page 12/12